Abstract: A signal equalizer that employs micro-electromechanical machine devices for the tap weight controllers. The equalizer includes a substrate on which is formed a forward transmission line rail and a return transmission line rail. A cantilever stanchion is also formed on the substrate that runs parallel with the transmission line rails. A series of spaced apart cantilevers are pivotally mounted to the cantilever stanchion, and extend over the transmission line rails to define a gap therebetween. A weight tap line is coupled to each cantilever, and is responsive to a DC weight signal that controls the position of the cantilever to set the gap between the cantilever and the transmission line rails. A distorted signal is coupled from the forward transmission line rail to the return transmission line rail through the cantilevers.

Abstract: A frequency offset estimator is employed that estimates the frequency offset in signal frames that include only binary Phase-Shift Keying (BPSK) carriers in OFDM systems. Specifically, the offset frequency estimator takes advantage of those OFDM systems in which some OFDM symbols only have carriers with either zero or the BPSK constellations. In many WLAN systems such as the system described in standard IEEE802.11a, transmission frames include only BPSK symbols, which are used for training and other services. By making use of these BPSK symbols in each frame, a very accurate estimate of frequency offset can be obtained. By advantageously employing the frequency offset estimator of this invention, a carrier recovery system can achieve high performance even under strong ISI and low SNR. In a specific embodiment of the invention, BPSK carriers spread to be on a line in a complex plane at an angle to the real axis.

Abstract: A method for transmitting a stream of data symbols in a multiple-input/multiple-output (MIMO) wireless communications system including Nr transmitting antennas. The stream of data symbols is first demultiplexed into M sub-streams, where M=Nr/2. Then, space-time transmit diversity encoding is applied to each sub-stream to generate a pair of transmit signals. Power is allocated dynamically to each transmit signal of each pair of transmit signals according to a corresponding feedback signal received from a receiver of the transmit signal. The feedback signal including a ratio of magnitude sums of channel coefficients for channels used for the transmit signals.

Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: A method for synchronizing counters in a terminal device, such as a cable modem in a DOCSIS-based system, with those of an administrative device, such as a headend. A cable modem advances its frame counter. With each increment of the frame counter, the cable modem's minislot counter advances by an amount equal to the number of minislots per frame. Likewise, with each increment of the frame counter, the cable modem's timestamp counter is incremented by the number of timestamps per frame. This continues until the counters at the cable modem are within one frame of the headend's counters. The minislot counter is then incremented. With each increment of the minislot counter, the timestamp counter is incremented by an amount equal to the number of timestamps per minislot. This continues until the cable modem's counters are within a minislot of the headend's counters. The timestamp counter is then incremented until the cable modem's counters match those of the headend.

Abstract: A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

Abstract: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Abstract: Detection for a MIMO (multiple-input, multiple-output) wireless communications system with symbols iteratively detected in subsets with maximum likelihood hard decisions within subsets. Previously detected subsets of symbols are used to regenerate corresronding input signals for interference cancellation. With a 4-transmitter antenna, 4-receiver antenna system, two subsets of two symbols are possible with the first two symbols detected with zero-forcing or MMSE soft estimates which feed maximum likelihood hard decisions; and the hard decision for the first two symbols are used for interference cancellation followed by zero-forcing or MMSE soft estimates for the second two symbols which then feed further maximum likelihood hard decisions.

Abstract: A device of dynamic communication of information allows, on the average, non-integer bits per symbol transmission, using a compact code set or a partial response decoding receiver. A stream of selectable predetermined integer bits, e.g., k or k+1 data bits, is grouped into a selectable integer number of bit vectors which then are mapped onto corresponding signal constellations forming transmission symbols. Two or more symbols can be grouped and further encoded, so that a symbol is spread across the two or more symbols being communicated. Sequence estimation using, for example, maximum likelihood techniques, as informed by noise estimates relative to the received signal. Each branch metric in computing the path metric of a considered sequence at the receiver is weighted by the inverse of the noise power. It is desirable that the constellation selection, sequence estimation and noise estimation be performed continuously and dynamically.

Abstract: A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal (yk), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Zs) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (b1s+1)/(a2s2+a1s+1) or (1?Vc)+VcPF(s) where Vc is adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a?k) as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.

Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.

Abstract: A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase error. The timing phase error is then averaged and controls a phase locked loop (PLL). This PLL in turn controls a voltage-controlled oscillator, which handles the modem receiver timing. A centroid calculation can be included to bias the voltage-controlled oscillator to push the equalizer coefficients back to the ideal position. The system can be implemented in either a point-to-point modem environment or a multi-point environment, for example, but not limited to, MVL or DMT. The voltage-controlled oscillator may also be implemented to control transmitter timing, so that the central office modem and the remote modem will operate more-or-less synchronously, reducing the need for large equalizer corrections at either end.

Abstract: A receiver/transceiver includes N pieces of receiving antennas, a propagation path characterization estimator, a weight generator for interference canceller, an array processing interference canceller, a weight generator for signal estimator, a signal estimator, a transmission signal classification apparatus, and a decoding order decision apparatus. The antenna inference elimination circuit eliminates only signal component relating to transmission signal component which does not belong to groups. The signal estimator performs separation and decoding of the transmission signal belonging to the group. The transmission signal classification apparatus classifies the transmission signals from sets of the transmission antennas in which a cross-correlation value of the vector is larger than a threshold value, into one group, and classifies the transmission signal in which the cross-correlation value is smaller than the threshold value, into another group.

Abstract: First and second transmission paths are provided between a first port to which an antenna is connected and a second port to which a transceiving circuit is connected. First to fourth reception filters, an amplifier circuit, and first to fourth hybrid circuits are provided on the first transmission path. A reception signal from the antenna is transmitted from the first port to the second port via the first hybrid circuit, the first and second reception filters, the second hybrid circuit, the amplifier circuit, the third hybrid circuit, the third and fourth reception filters, and the fourth hybrid circuit in this order. This reception signal does not return to the amplifier circuit, whereby the reception signal is prevented from oscillating due to positive feedback.

Abstract: A flexible scheduling method with tunable throughput maximization and fairness guarantees in resource allocation is required and suitable for high-rate packet data and other services. Our inventive method, named Alpha-Rule, employs a control variable ?, that permits dynamic and/or real-time adjustment/tradeoff between aggregate throughput, per-user throughput, and per-user resource allocation. Our method advantageously operates in conjunction with Multiple-Input Multiple-Output techniques such as Space-Time Block Coding (STBC), Bell Labs Layered Space-Time (BLAST) and others, while offering greater flexibility than existing scheduling techniques, e.g., max-C/I or Proportionally Fair (PF).

Abstract: A method of performing data detection for a global positioning system (GPS) receiver is disclosed. The method includes receiving a first in-phase (I) reference signal during a first time interval and receiving a first quadrature (Q) reference signal during a first time interval. The method also includes receiving a second in-phase (I) reference signal during a second time interval and receiving a second quadrature (Q) reference signal during a second time interval. The method further includes computing a first sum of the first I reference signal and the second I reference signal, computing a second sum of the first Q reference signal and the second Q reference signal, computing the difference of the first I reference signal and the second I reference signal; and computing the difference of the first Q reference signal and the second Q reference signal.

Abstract: A technique for pre-compensating a digital bit stream for distortion imposed by a transmission path includes adjusting the level of the digital bit stream on a bit-by-bit basis in a manner that simulates the effects of a filter having a transfer function that is substantially the inverse of that of the transmission path. The technique includes generating a plurality of reference levels that correspond to correcting levels of the digital bit stream and switching these levels to the transmission path at high speed in response to the current bit of the digital bit stream and at least one previous bit. When used in an automatic test system, the technique improves signal transmission and reduces jitter, therefore allowing jitter of devices under test to be measured more accurately.

Abstract: A digital circuit configured to spread a clock train spectrum includes a clock configured to generate the clock train, and a variable divider configured to divide the frequency of the clock train by a temporally-varying-divider value to modulate the clock train and generate a dithered clock train. The circuit further includes a first accumulator configured to accumulate the dithered clock train to generate a frequency modulation waveform, and a second accumulator configured accumulate the frequency modulated waveform to generate a phase modulation signal. The circuit further includes a phase-value calculator configured to calculate the temporally-varying divider value based on the phase modulation signal; and a closed-loop control circuit configured to track and filter the modulation of the dithered clock train to generate a second clock train that is the spread spectrum of the first mentioned clock train.

Abstract: A precision timing generator and an associate method provide a precise clock signal based on a reference clock signal. Using the reference clock signal in a phase locked loop or delay locked loop, a number of clock signals of equal frequency are generated separated consecutively by a known phase. Two of these clock signals of consecutive phases are selected for interpolation for higher precision according to predetermined weights. The resulting interpolated clock signal has a phase offset that is intermediate between the selected clock signals in proportion to the predetermined weights. In one implementation, a second interpolated clock signal is created by selecting and weighting a second group of clock signals using independent selection and weights. The two interpolated clock signals are then combined by logic operations to provide a precise clock signal of predetermined duty cycle and phase.

Abstract: The feedback structure of a frequency domain decision feedback equalizer is implemented in the frequency domain, rather than in the time domain. Advantageously, this permits the synthesis of long feedback filters with a much smaller increase in receiver complexity than is the case when the feedback structure is illustratively implemented in the time domain. Adaptation of the characteristics of the feedback structure of the frequency domain equalizer (as well as its feedforward structure) is carried out based on tentative symbol decisions that are fed back on a block basis. Although possibly rendering the receiver more susceptible to channel estimation errors, this approach renders the receiver capable not only of the post-cursor intersymbol interference cancellation afforded by a standard DFE, but pre-cursor intersymbol interference cancellation, as well, helping to offset any impact of increased channel estimation errors.