Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

Abstract: A high frequency compensator configured to compensate high frequency component of a digital audio signal comprising a down sampler configured to perform ½ down-sampling for the digital audio signal. An up sampler is configured to perform double up-sampling for an output signal of the down-sampler. A digital low-pass filter is configured to filter an output signal of the up sampler, and to output the filtered digital audio signal.

Abstract: A non-integer CIC interpolation filter is provided for use in sigma-delta digital-to-analog systems, which realizes non-integer interpolation but eliminates the need for coupling of the integrators in the output domain. The present non-integer interpolation filter provides for more attenuation to all of the aliases of the input signal and has eliminated the need of complex computations.

Abstract: A digital modulator includes a quantizer and a mapper. The quantizer converts a dithered signal value to a voltage. The mapper provides a modulated signal based on the voltage received from the quantizer. The mapper may maintain a substantially identical average centroid for modulated signals provided by the mapper. In an aspect, the mapper is included in a feedback of the digital modulator. The digital modulator may include any number of mappers. For example, a mode selection switch may select one of a plurality of mappers to map a voltage level received from the quantizer to a respective digital sequence.

Abstract: Systems and methods implemented in a multi-bit digital noise shaper for reducing or eliminating undesirable transient response when the noise shaper exits a clipping state. In one embodiment, the noise shaper includes a quantizer, a filter, and a filter control unit that detects clipping in the quantizer and dynamically adjusts the allowable range of the internal state values of the filter. In one embodiment, a clipping mechanism is provided for each state value within the filter to clip the state value if it exceeds a corresponding clipping level. The clipping level for each state value is lower when the quantizer is clipping, and higher when the quantizer is not clipping. The clipping level for each state value may be transitioned either immediately or gradually from a current level to a target level (which is lower when the quantizer is clipping, and higher when the quantizer is not clipping.

Abstract: An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.

Abstract: Disclosed is an analog-to-digital converter circuit that includes a reference circuit for applying reference voltages to comparators that compare the reference voltages with the output of the buffer circuit.

Abstract: A data serializer includes a data aligner, two N-bit shift registers, a 2-1 multiplexer, and a driver, wherein N is the number of parallel input data bits. Data is received and aligned by the data aligner, which is arranged to drive odd and even data lines to a respective one of the N-bit shift registers. One N-bit shift register is arranged to operate with a clock that is 180 degrees out of phase with respect to the other N-bit shift register. The frequency of the clock for each N-bit shift register is related to an input clock frequency by a factor of N/2. The multiplexer is arranged to alternate the selection of the N-bit shift registers to provide the output signal. The output of the multiplexer corresponds to a high-speed serial data stream that can be provided to a driver such as LVDS, DVI, PPDS or RSDS drivers.

Abstract: Data throughput rates are increased in an optical fiber communication system without requiring replacement of the existing optical fiber in a link. Channel throughput is increased by upgrading the components and circuitry in the head and terminal of an optical fiber communication system link. Aggregate throughput in a fiber optic link is increased beyond the range of conventional Wavelength Division Multiplexed (WDM) upgrades, while precluding the necessity of replacing existing fiber plants. The increase in system throughput is achieved by using advanced modulation techniques to encode greater amounts of data into the transmitted spectrum of a channel, thereby increasing the spectral efficiency of each channel. This novel method of increasing transmission capacity by upgrading the head and terminal of the system to achieve greater spectral efficiency and hence throughput, alleviates the need to replace existing fiber plants.

Abstract: In the decoder of binary arithmetic code of the present invention, the decoding and reverse binarization of arithmetic code are separated and a large intermediate buffer is interposed. The decoding of arithmetic code is first carried out at the time of input of a stream, whereby the arithmetic code can be decoded at the maximum input bit rate of the decoder. The obtained binary symbol string is first held in the intermediate buffer, following which the reverse binarization from the binary symbol string to multivalued symbols is carried out matched to the processing of the block decoder of the next stage.

Abstract: Methods, algorithms, software, circuits, architectures, and systems for conditionally encoding information and processing conditionally encoded information. The present invention takes advantage of codes where most randomly selected data units fulfill the coding constraints. Thus, only those data units that need encoding (i.e., that do not fulfill coding constraints) are encoded, and those data units that do not need encoding (i.e., that fulfill coding constraints) are not encoded. By doing so, one may increase the density, bandwidth and/or gain of data communications, increase the error checking and/or correcting capabilities of a data communications system, and/or reduce interference in a multi-user system.

Abstract: A network device capable of transmitting data includes a processor, an encoder and a port. The encoder encodes the data using a known valid dictionary while constructing a new dictionary over an epoch of data. A network device capable of receiving encoded data is also disclosed. The network device includes a processor, a port and a decoder. The decoder is operable to decode the data using a known valid dictionary, while constructing a new dictionary over the epoch of data. When a valid dictionary has been constructed, the receiving device notifies the transmitting device.

Abstract: The present invention comprises a test set-up (20) and method of testing a correlated double sampling circuit (CDS) (24) by using a sinusoidal test signal (22) for measuring linearity. The present invention generates a sinusoidal signal with two accurate and known levels at two different time points, as an input to the CDS. The cosinusoidal output of the CDS is then processed using an ADC (60) and processor (62) to check the functionality and linearity of the CDS circuit under test.

Abstract: A hardware-implemented Huffman decoder converting Huffman-encoded data to raw data using logic gates to implement logic states. The logic states include IDLE, COEFF_READ, COEFF_WRITE, HUFF_ADDR_LOG, HUFF_ADDR_PHY, AMP_CAL, and EOB_RUN13 GEN. IDLE state transfers to COEFF_READ or AMP_CAL states according to eob_run, ac_first_scan, and ss signals, COEFF_READ state transfers to HUFF_ADDR_LOG or AMP_CAL states according to ac_first_scan, ac_refine_scan, eob_run, new_ac_nonzero_coeff, and dc_refine_scan signals. COEFF_WRITE state transfers to AMP_CAL or COEFF_READ states according to ac_first_scan, coeff_index, zero_run, and eob_run signals. HUFF_ADDR_LOG state transfers to HUFF_ADDR_PHY state and HUFF_ADDR_PHY state transfers to AMP_CAL or EOB_RUN_GEN states according to ac_first_scan and ac_refine_scan signals.

Abstract: Context-based adaptive arithmetic coding and decoding methods and apparatuses with improved coding efficiency and video coding and decoding methods and apparatuses using the same are provided. The method for performing context-based adaptive arithmetic coding on a given slice in an enhancement layer frame of a video signal having a multi-layered structure includes steps of resetting a context model for the given slice to a context model for a base layer slice at the same temporal position as the given slice, arithmetically coding a data symbol of the given slice using the reset context model, and updating the context model based on the value of the arithmetically coded data symbol.

Abstract: System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.

Abstract: A digital-to-analog converter (DA and the method thereof are disclosed. The DAC receives a digital signal with (M+N) bits, and a reference voltage unit sequentially outputs 2M+N reference voltages through the 2N output terminals thereof according to at least N timing signals. Afterwards, a control unit outputs at least a reference voltage to a decoding unit according to the above-mentioned N timing signals and the N bits of the digital signal. In the end, the decoding unit selects one of the signals produced by the control unit as the analog signal for output according to the M bits of the digital signal.

Abstract: For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.

Abstract: An implantable medical device uses a sampling scheme to obtain digital representation from analog signals. The analog signals represent intracardiac activity. Generally, a detector detects the amplitude of the analog signals and generates first and second difference signals. The first difference signal is generated after detection of significant changes in the analog signal amplitude. The second difference signal is generated upon confirmation of the absence of significant changes in the analog signal amplitude over a predetermined period of time. A frequency selection is implemented to select the sampling frequency based on the first and second difference signal.

Abstract: Methods and systems for implementing high-performance data converters remove analog technology bottlenecks and provide higher converter resolution and higher speed using lower-performance converters and processing in the frequency domain. The method comprises transforming a time domain input signal into a frequency domain signal in a digital form, processing the frequency domain signal and the input signal using at least two lower-performance data converters in order to obtain at least two processed signals, and recombining the at least two processed signals to obtain a final output signal from the high-performance converter. The processing may include dividing the frequency domain into at least two frequency domain parts, one related to a low-resolution signal to noise ratio (SNR) and the other related to a high-resolution SNR, and using frequency information resulting from the division to obtain the at least two processed signals.