Abstract: A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

Abstract: A reference generator circuit has a resistor string between the potentials of the power supply voltage that is partitioned into a top string, a middle string, and a bottom string. PFET devices are used to couple the positive power supply voltage a selected node of the top string in response to first control signals and complementary second control signals are used to control NFET devices that couple the ground power supply voltage to a selected node of the bottom string. If a resistor is effectively removed from the top string a corresponding resistor is effectively added in the bottom string keeping the total resistance in the resistor string substantially constant. A pass gate network is used to select between nodes of the middle string as a vernier for generating small step sizes.

Abstract: A Continuous-Time Delta-Sigma Analog-to-Digital Converter (CT??ADC) for a radio frequency (RF) receiver employing a 200 kHz IF realizes an optimal signal-to-noise ratio using a programmable resonator that is set to resonate at 200 kHz. The programmable resonator is operably coupled to receive both an analog input signal at a low IF of 200 kHz and an analog feedback signal. From the analog input signal and the analog feedback signal, the programmable resonator produces a resonate signal at the low IF, and provides the resonate signal to a quantizer. The quantizer produces a digital output having a digital value coarsely reflecting an amplitude of the analog input signal. The CT??ADC further includes at least one programmable digital-to-analog converter (DAC) operably coupled to receive the digital output and to convert the digital output into the analog feedback signal provided to the programmable resonator.

Abstract: A continuous-time band-pass ?? AD modulator subtracts an analog signal from a DA converter from an inputted analog signal, outputs an analog signal having a subtraction result to an AD converter via a continuous-time analog band-pass filter, outputs a digital signal from the AD converter to the DA converter, and outputs the same digital signal as a digital signal subjected to a band-pass ?? AD modulation processing. The highest input frequency “fin” of the inputted analog signal is substantially set to three-fourths of a sampling frequency “fs”. The DA converter is configured to convert the inputted digital signal into the analog signal, and outputs the analog signal, which is inverted or not in response to a value of the inputted digital signal and has an amplitude of substantially zero and a gradient of substantially zero at a timing k/(2fs).

Abstract: A sound codec including a compression portion and a decompression portion. The compression portion separates the incoming sound packet bandwidth into frequency sub-bands using a bank of infinite impulse response (IIR) filters. In accordance with the invention, the lower frequency signals are divided into more sub-bands than the higher frequency signals. Once the signals are divided into sub-bands, each sub-band signal is quantized. The resulting signals of all of the quantized sub-bands are then sent out over a communications link along with the filter state at the end of each sound packet. The decompression portion recombines the individual sub-band signals together (using a bank of infinite impulse response (IIR) filters) to form the audio data using the filter states to configure the reconstruction.

Abstract: A microwave frequency deflection cell analog to digital converter is provided. The phase velocity of an optical wave is effectively reduced to that of a microwave frequency electro-magnetic signal in an optical deflector. The electro-optic effect is used for a controlled deflection of an optical beam. The angle of beam deflection varies in accordance with an applied voltage, which may be a signal in the microwave frequency range. A device of the invention includes a birefringent crystal having transmission line conductors arranged to create an electric field in the crystal in response to an applied voltage, and mirrors arranged to create a multi-bounce path through the crystal for a light beam directed into the crystal on an entrance path that is non parallel to the mirrors. The multi-bounce path effectively slows the velocity of the optical wave to that of the voltage wave, permitting deflection or modulation of the beam by microwave frequency electrical signals.

Abstract: A system (100) and method (200) of combining codewords is provided. The system can include a splitter (120) for splitting a first codeword (110) into a most significant bits part MSP (112) and a least significant bits part LSP (114), a combiner (130) for combining the MSP of the first codeword with a second codeword to produce a first group (132), and a concatenator (140) for concatenating the first group with the LSP to produce a second group (134), and multiplexing the first group with the second group to produce a multiplexed codeword (150). Bit-errors in the LSP correspond to decoding errors only in a codeword associated with the LSP, and not to decoding errors in other codewords.

Abstract: A sigma delta analog to digital converter of the type adapted to be connected to a capacitive current input device, comprises: a sigma delta modulator having an input; and a flying capacitor constructed so as to be connected between the input of the sigma delta modulator and the capacitive current input device. In a preferred embodiment, the converter includes an input stage having an input coupled to the flying capacitor; a feedback path; a digital to analog converter (DAC) disposed in the feedback path and having a DAC output; and a DAC output capacitor and a second switch for alternately switching the DAC output capacitor between a first connection so as to transfer a signal from the output of the digital to analog converter to the DAC output capacitor and a second connection so as to transfer a signal from the DAC output capacitor to the input of the sigma delta modulator.

Abstract: The quantizer (2?) has an input network (5) which generates N different drive signals (Vij) as a function of the quantizer input signal (VI+?VI?). The input network (5) is designed in such a way that a value of the respective drive signal (Vij) which is greater than a comparison value indicates that the quantization threshold which is associated with the respective drive signal (Vij) has been exceeded. Furthermore, the quantizer has a switching network (9), which associates the N drive signals (Vij) with the N comparator inputs.

Abstract: In a first-order complex band-pass filter, multiplexers are alternately switched over between time intervals of phases A and B, where the multiplexers includes two multiplexers provided at input and output stages, and a multiplexer provided in a feedback circuit of each of first-order filters and being switching over whether to invert a sign of a feedback signal. Then in a circuit part sandwiched between the multiplexers, a processing performed by an I circuit part and a processing performed by a Q circuit part are alternately switched over so that a sign of a signal inputted to an adder is inverted.

Abstract: Disclosed is a signal processing circuit which outputs a digital word corresponding to a current source controlled by a physical response. The signal processing circuit includes an analog integrated circuit for generating an analog signal in response to a time varying reference signal and a signal corresponding to the current source controlled by the physical response, a reference signal generator for generating a reference signal, a comparator for comparing the analog signal with the reference signal, an output circuit for generating the digital word indicating a time interval defined by a start signal and an end signal indicating a transition of an output of the comparator, and a controller inactivating the comparator in response to the end signal.

Abstract: A high-speed, high-accuracy DAC has multiple current switches. Each current switch includes a current source that provides a reference current, first and second circuit elements that couple to the current source, and first and second transistors that couple to the first and second circuit elements, respectively. The first transistor provides the reference current to a first output when enabled, and the second transistor provides the reference current to a second output when enabled. The first and second circuit elements provide source degeneration for the first and second transistors, extend the linear operating region for these transistors, and may be implemented with either transistors that are always turned on or resistors. The first and second transistors and the first and second circuit elements may be P-channel field effect transistors (P-FETs), N-channel field effect transistors (N-FETs), or transistors of some other type.

Abstract: A technique includes providing a butter to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer. The techniciue may be used with a wireless system that includes a digital signal processor, a buffer, a wireless interface and a switch. The buffer receives data from the digital signal processor in response to an active mode of the digital signal processor. The switch selectively couples a terminal of the wireless interface to the buffer in response to a determination of a status of the buffer.

Abstract: A multi-bit sigma-delta analog-to-digital converter (ADC) has a single-ended input for receiving an analog input signal. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a multibit digital feedback signal from a Flash ADC. The feedback current is summed with the input signal with the feedback current. The summed signal is integrated on a continuous-time basis. The IDAC is selectively connectable to the summing node via a first path and a second path. The first path transmits current from the IDAC to the summing node with a first polarity and the second path transmits current from the IDAC to the summing node with an inverted polarity. This can reduce flicker noise and can allow the converter to operate without any mid-scale biasing current sources.

Abstract: An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.

Abstract: The present invention provides a method and system for converting an input code into an output code. The method includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, respectively; and merging the output code subsets to generate the output code. The system includes a splitter, for determining a plurality of input code subsets of the input code; a mapper, coupled to the splitter, for converting the input code subsets into a plurality of output code subsets, respectively; and a merger, coupled to the mapper, for merging the output code subsets to generate the output code.

Abstract: A method and apparatus for an image canceling digital-to-analog converter is disclosed. Up-sampling and noise shaping is used to produce a stream of digital sample values at a relatively higher sampling rate than the sampling rate of the digitized input samples, each higher sampling rate sample having fewer bits than the original samples. The higher sampling rate stream is then distributed for sequential conversion by multiple digital-to-analog converters each operating at a lower sampling rate. The outputs of the converters are then combined to form a combined output signal. Most spectral images normally observed in a standard or conventional DAC are attenuated in the combined output signal of an embodiment in accordance with the present invention. Any spectral images that remain are further from the signal of interest, permitting the use of lower cost filtering.

Abstract: A method and apparatus are provided for converting an analog audio signal into digital data. A signal with small magnitude more closely approximates the original signal by varying an amplification ratio depending on the magnitude of an input analog audio signal so that the input analog audio signal can be amplified to maximum possible amplitude corresponding to the number of bits that can be stored when converting the analog audio signal into digital data. The amplitude of an amplified analog audio signal also can be reconstructed if necessary, thereby providing better sound quality with the same level of sound.

Abstract: Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. The generated output code words are sequentially connected into a sequence of the generated output code words which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number between 7 and 12.