Patents Examined by Jeff Vockrodt
  • Patent number: 6975022
    Abstract: A device containing a flat member is provided, having a pattern for a bonding pad, a wiring, and an electrode, by half-etching through the flat member.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 13, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 6852595
    Abstract: Methods of manufacturing flash memory cells. During a cleaning process after an etching process for forming a control gate is performed, polymer remains at the sidewall of a tungsten silicide layer. Therefore, the sidewall of the tungsten silicide layer is protected from a subsequent a self-aligned etching process. In addition, upon a self-aligned etching process, the etch selective ratio of the tungsten silicide layer to a polysilicon layer is sufficiently obtained using a mixed gas of HBr/O2. Therefore, etching damage to the sidewall of the tungsten silicide layer can be prevented. As a result, reliability of the process and an electrical characteristic of the resulting device are improved.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: February 8, 2005
    Assignee: Hynix Semiconductor
    Inventor: In Kwon Yang
  • Patent number: 6835601
    Abstract: An apparatus and method for manufacturing substrate elements includes providing a mother substrate, and forming a plurality of through-holes on first lines and second lines opposing each other across sections on the mother substrate. The sections define each of the substrate elements to be formed. The through-holes on the first lines are disposed alternately with respect to the through-holes on the second lines. Electrodes are also provided on the principal plane of the mother substrate and on the inner surfaces of the through-holes. Then, the mother substrate is cut along cut lines in the vertical and horizontal directions.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: December 28, 2004
    Assignee: Murata Manufacturing Co., LTD
    Inventor: Masaya Wajima
  • Patent number: 6815239
    Abstract: Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. These five methods accommodate the fabrication of an optical interference multilayer, which improves the image quality of the reflected light. These five methods are: Silicon Dioxide Posts by Wet Etching. Amorphous Silicon Posts by Plasma Etching. Silicon Nitride Posts by Plug Filling. Insulation Material Posts by Lift-off. Polyimide Posts by Photosensitive Etching.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sik On Kong, Rajan Rajgopal, George Wong
  • Patent number: 6812492
    Abstract: The present invention relates to a method of fabricating a lightly-doped drain (“LDD”) thin film transistor of a coplanar type wherein the transistor has an LDD region of uniform resistance formed by locating a peak point of dopant in an active layer covered with an insulating layer wherein the dopant is very lightly distributed. The present invention further includes the steps of forming an active layer on an insulated substrate, forming an insulating layer covering the active layer, forming a gate electrode on the insulating layer over the active layer, doping lightly the active layer as a target with impurities, forming a gate insulating layer by patterning the insulating layer to be extended out of the gate electrode, and forming a source region and a drain region in portions of the active layer which are exposed by the step of forming the gate insulating layer.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: November 2, 2004
    Assignee: LG Philips LCD Co., Ltd.
    Inventor: Dong-Wook Choi
  • Patent number: 6800516
    Abstract: The problem of gate oxide damage as a result of electrostatic discharges has been overcome by including within the drain of the ESD protection device a region having very high defect density. Its depth within the drain is such that no action occurs when applied voltages are low. However, when a high voltage is applied, the depletion layer grows wide enough to touch this region thereby allowing substantial current flow into the substrate which results in lowering the voltage to a safe level. The high defect density region is formed through ion implantation of relatively heavy ions such as germanium. This is done after completion of the normal manufacturing process including SALICIDATION, no significant heating of the device after that being permitted.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: October 5, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ling Chan, Fu-Liang Yang, Yi Ming Sheu
  • Patent number: 6797582
    Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: September 28, 2004
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Michael P. Chudzik, Rajarao Jammy, Christopher C. Parks, Kenneth T. Settlemyer, Jr., Radhika Srinivasan, Kathryn H. Varian
  • Patent number: 6797584
    Abstract: First and second transistors are formed on the principal surface of the semiconductor substrate, and an insulating film is formed over the principal surface of the semiconductor substrate so as to cover the first and second transistors. A first storage node is connected to the first transistor and has a first enclosed wall structure which is formed over the insulating film and encloses a surface region of the insulating film. A second storage node is connected to the second transistor and has second enclosed wall structure which is formed over the insulating film and surrounds the first enclosed wall structure. A capacitor insulating film covers the first and second enclosed wall structures, and a cell-plate is formed on the capacitor insulating film.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: September 28, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masahiro Yoshida, Kazuya Suzuki
  • Patent number: 6798052
    Abstract: An electronic device (38) for mounting on a curved or flexible support (42) and a method for fabrication of the same. The electronic device comprises a layer (2) of rigid material having electronic components on its upper surface. Weakened regions (6) of the rigid layer (2) define contiguous portions of the rigid layer, and flexible connectors (16) extend between components on different portions. The rigid layer (2) can be fractured along the weakened regions (6) to afford flexibility.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: September 28, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Peter W. Green
  • Patent number: 6794211
    Abstract: The light emitting diode includes an intermediate layer made of non-single crystalline material between single crystalline layers. By the intermediate layer, the boundary characteristic between the single crystalline layers may be improved and the defect caused by the lattice mismatch can be decreased, so that the brightness and forward voltage characteristics can be improved.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: September 21, 2004
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myeong Seok Oh, Sung Wook Lim, Jeong Hwan Ahn
  • Patent number: 6790739
    Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
  • Patent number: 6787400
    Abstract: An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Stephen R. Porter, Manny K. Ma, Stephen Casper, Kevin Duesman
  • Patent number: 6787450
    Abstract: A method is described for filling of high aspect ratio contact vias provided over silicon containing areas. A via is formed in an insulating layer over the silicon containing area and a silicide forming material is deposited in the via. A silicide region is formed over the silicon containing area, the silicide forming material is removed from the via leaving the silicide region. The via is then filled with a conductor using an electroless plating process.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Paul A. Morgan
  • Patent number: 6777304
    Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 17, 2004
    Assignee: International Business Machines Corporation
    Inventors: Fariborz Assaderaghi, Harold Wayne Chase, Stephen Larry Runyon
  • Patent number: 6770556
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 3, 2004
    Assignee: Applied Materials Inc.
    Inventors: Wai-Fan Yau, David Cheung, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Yu
  • Patent number: 6770927
    Abstract: The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: August 3, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Chih-Chen Cho, Richard H. Lane, Charles H. Dennison
  • Patent number: 6770532
    Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: August 3, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
  • Patent number: 6764875
    Abstract: A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: July 20, 2004
    Assignee: Silicon Light Machines
    Inventor: James Gill Shook
  • Patent number: 6764964
    Abstract: A method for forming patterns of a semiconductor device is disclosed which inhibits collapse of photoresist patterns in photoresist pattern-forming processes of the semiconductor device by forming micro-bends in an anti-reflective film to increase the contact area between a photoresist and the anti-reflective film and, simultaneously prevents critical dimension (CD) alteration of the photoresist pattern by creating micro-bends and double-laminating of anti-reflective films with different refractive indices and light-absorbencies.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-sun Hwang, Jae-chang Jung, Sung-koo Lee, Chcol-kyu Bok, Ki-soo Shin
  • Patent number: RE38727
    Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickwise direction of the I-type layer.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: April 19, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki