Abstract: Presented is a method of conformally coating a light emitting semiconductor structure with a phosphor layer to produce a substantially uniform white light. A light emitting semiconductor structure is coupled to a submount, a first bias voltage is applied to the submount, and a second bias voltage is applied to a solution of charged phosphor particles. The charged phosphor particles deposit on the conductive surfaces of the light emitting semiconductor structure. If the light emitting semiconductor structure includes a nonconductive substrate, the light emitting semiconductor structure is coated with an electroconductive material to induce phosphor deposition. The electrophoretic deposition of the phosphor particles creates a phosphor layer of uniform thickness that produces uniform white light without colored rings.

Abstract: The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

Abstract: An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

Abstract: A method of forming a floating gate electrode of a cell of a flash memory device having an interval less than a critical dimension (CD) in a conventional photolithographic process, in which the reliability of a dielectric layer does not deteriorate and damage to a floating gate electrode during etching is prevented, is provided. According to the present invention, a protective layer formed of a material having a high etching selectivity with respect to a device isolation layer and a doped polysilicon layer is formed on the upper surface of the doped polysilicon layer forming the floating gate electrode. The protective layer is partially etched and includes a recess. Next, a material layer for forming a spacer, which is formed of a material having a high etching selectivity with respect to the device isolation layer and the doped polysilicon layer, is formed on the upper surface of the protective layer and is etched back, thus forming the spacer.

Abstract: A low temperature ozone-enhanced oxidation process is presented whereby amorphous high dielectric constant film devices are subject to oxidation processes at temperatures whereby crystallization of the amorphous high dielectric constant film is avoided, thereby lowering leakage currents and reducing the required thickness to achieve an equivalent SiO2 thickness (EOT)

Abstract: An improved structure and method are provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various intergrated circuit devices located on the opposing surfaces of the silicon interposer.

Abstract: A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

Abstract: A logic/flash memory manufacturing process generates recesses used for isolation in a self-aligned silicide process, in some specific location in the substrate, to avoid short circuits. The problem caused by misaligned borderless contact is avoided. Moreover, Very Large Scale Integration (VLSI) structure integration is improved without extra mask layers.

Abstract: A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.

Abstract: A gateway or circuit barrier capacitor incorporated in a semiconductor die structure in lieu of a discrete capacitor employed with such a die in a Chip on Board assembly such as a single in-line memory module (SIMM). The capacitor may comprise a single layer with laterally adjacent, dielectrically separated electrode traces, or a more traditional vertically superimposed electrode design with an intervening dielectric layer. The capacitor is preferably formed using the existing fabrication process for the die by altering a photoresist mask to define the electrode traces in the same step as other conductors, such as bond pads, are formed.

Abstract: A method of transferring elements to be used in an assembly by placing elements in regions of a template. In one example of a method, each of the elements includes a functional component. A template holding a plurality of elements is then pressed into the receiving substrate by attaching at least one side of the template holding the elements onto the receiving substrate.

Abstract: A method is disclosed for aligning structures on first and second opposite sides of a wafer. First one or more transparent islands are formed on the first side of the wafer at an alignment location. The transparent islands have an exposed front side and a rear side embedded in the wafer. At least one alignment mark is formed on the front side of the transparent island. An anisotropic etch is performed through the second side of said the to form an opening substantially reaching the back side of the transparent island. A precise alignment is then carried out on the alignment mark through the opening and the transparent island. In this way a very precise alignment can be carried out on the back side of the wafer for manufacturing MEMS structures.

Abstract: An ultra-thin body SOI MOSFET transistor and fabrication method are described which provide extended silicide depth in a gate-last process. The method utilizes the fabrication of a dummy gate, comprising insulation, which is replaced with an insulated gate after implantation, annealing, and the formation of silicide so that diffusion effects are reduced. By way of example, dummy gate stacks are created having insulating upper segments. Silicon is deposited on the wafer and planarized to expose the insulating segment. The junction is formed by implantation followed by annealing to recrystallize the silicon and to activate the junction. Silicide is then formed, to a depth which can exceed the thickness of the silicon within the SOI wafer, on the upper portion of the silicon layer. The segment of insulation is then removed and a gate is formed with a gate electrode insulated by high-k dielectric.

Abstract: A method for manufacturing a semiconductor laser diode is described. The method for manufacturing a semiconductor laser diode includes sequentially forming a buffer layer, a first clad layer, a first waveguide layer, an active layer, a second waveguide layer, a second clad layer, and a cap layer on a substrate, patterning the cap layer, and patterning the second clad layer as a ridge structure by making the patterned cap layer as an upper layer, selectively forming a passivation layer for covering the second clad layer patterned as the ridge structure around the cap layer, and forming an electrode in contact with the cap layer on the passivation layer.

Abstract: A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon.

Abstract: A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiOx or SixNy overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.

Abstract: Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.

Abstract: A connection between a contact plug and an interconnect in a semiconductor device is disclosed. A contact plug is formed in a hole within an insulating film with its upper end generally in flush with a surface of the interlayer insulating film. An interconnect uses a laminated film structure that includes an aluminum film over the upper end of each of the contact plug.

Abstract: A method for fabricating a lower plate of a capacitor of a semiconductor device, including forming a planarization layer on a semiconductor substrate, forming a conductive plug in the planarization layer, forming a first nitride film on the planarization layer and the top surface of the conductive plug, forming a first oxide film on the top surface of the first nitride film with a trench in the first oxide film around the conductive plug, forming a second nitride film in the trench, removing the first oxide film, forming a second oxide film, exposing the top surface of the conductive plug, forming a silicon layer pattern on the top surface of the conductive plug and the side walls of the second oxide film, removing the second oxide film, forming silicon grains on the surface of the silicon layer pattern, and removing the second nitride film.

Abstract: There is disclosed a semiconductor device comprising a copper interconnect layer 7 where a copper film is buried in a concave in an insulating film 3 via a barrier metal film, wherein the copper interconnect layer 7 has a line/space ratio of 4.5 or less and an interconnect occupancy of 10 to 60%. It can effectively prevent dishing and erosion, as well as increase and dispersion in an interconnect resistance when forming damascene copper interconnects.