Abstract: In a ferroelectric integrated circuit, a hydrogen barrier layer comprising titanium or titanium nitride or both is formed over a metal oxide element to protect it from hydrogen degradation. After hydrogen annealing and other process steps causing hydrogenating or reducing conditions, the hydrogen barrier layer is removed in a two-step etching process. The first etch step is a dry etch, preferably a standard ion-mill etching process, which rapidly removes most of the hydrogen barrier layer. The second step is a wet, chemical etch, preferably using a solution containing NH4OH, H2O2, and H2O, which selectively removes remnants of the hydrogen barrier layer from the circuit by oxidizing a chemical element of the barrier layer. The metal oxide material preferably comprises a layered superlattice compound.

Abstract: A method of fabricating a semiconductor device includes a step of attaching a circuit substrate on a semiconductor wafer in alignment with each other, providing an electrical interconnection between the circuit substrate and semiconductor devices formed in the wafer, providing solder bumps on the circuit substrate, and dicing the semiconductor wafer together with the circuit substrate thereon along a scribe line.

Abstract: A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. This is due to the fact that each material has a dielectric constant that is different. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of two spacers at the sidewalls of the gate. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacers. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.

Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w

Abstract: A bonded wafer in which silicon wafers and an amorphous heat fusion bonding polyimide are used, a process for producing the same, and a substrate which is prepared by variously processing the bonded wafer.

Abstract: A manufacturing method for a semiconductor device in which, when a silicon oxide film on a semiconductor substrate is wet-etched for trench device isolation, no divot is formed at a device isolation end due to etching of a first insulating film of a trench isolation region to improve yield as well as reliability and productivity. A second insulating film (7 of FIG. 2) is formed and etched to leave a second insulating film 7a selectively in the rim of a isolation region where a divot is likely to be formed to prevent the divot from being formed by wet etching.

Abstract: A method of manufacturing an electronic device including an oxide film of perovskite-type, said method comprising the steps of forming on a base substrate a first conductive oxide film of perovskite type in an atmosphere of reduced pressure at a first temperature, and performing heat treatment on the first conductive oxide film in an oxidizing atmosphere containing oxygen at a second temperature which is higher than the first temperature.

Abstract: A process for forming a W-poly gate stack (110) comprising the steps of: (1) deposition of doped polysilicon (112) on a thin dielectric layer (108) covered substrate (102), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (114) and to remove excess nitrogen and (4) deposition of W layer (116). The stack layers are then etched to form the gate electrode (110).

Abstract: A trench storage dynamic random access memory cell with vertical transfer device can be formed in a wafer having prepared shallow trench isolation. Vertical transfer device is built as the deep trenches are formed. Using square printing to form shallow trench isolation and deep trenches, allows for scaling of the cell to very small dimensions.

Abstract: A barrier layer is included in an integrated circuit capacitor, between a conductive plug and a lower capacitor electrode. The barrier layer includes refractory metal and grain boundary filling material. The grain boundary filling material preferably is Ce, Zr, Y, Th, Hf, La, Al and/or oxides thereof, and is preferably less that 20 atomic percent of the barrier layer. The barrier layer can reduce and preferably prevent diffusion of oxygen, and can thereby reduce the leakage current and oxidation of the integrated circuit capacitor.

Abstract: A lead frame for ball grid array which is composed of a plurality of inner leads extending from outside to inside and having terminal ball bumps formed somewhere along them, characterized in that said terminal ball bumps are formed in at least two rows, with adjacent ones not overlapping in the lengthwise direction of the inner lead and said rows holding the bonding area between them. The bonding area may plated according to need. The lead frame can be produced in high yields without reduction in the number of pins. Disclosed also herein are a semiconductor device using said lead frame and a process for producing the same.

Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract: A MOS transistor has a gate electrode (33) having a T-shaped cross-section. The gate length is defined in a first structuring step by a spacer technique. The area of the gate electrode in the upper region is defined in a second structuring step. The MOS transistor can be produced with a channel length of less than 100 nm.

Abstract: A method of forming a semiconductor device assembly comprising forming a wire bump on at least one bond pad on the active surface of a semiconductor device and connecting one end of a wire to the wire bump using a wire bond. The wire bump may be flattened before connecting one end of a wire thereto.

Abstract: A method of forming a dual cylindrical capacitor on a semiconductor substrate having at least a device isolation structure and a transistor thereon is provided, wherein the transistor includes at least a gate and a source/drain region. A first insulation layer and a second insulation layer are formed on the substrate. An opening comprising an lower part penetrating through the first insulation layer and an upper part penetrating through the second insulation layer is formed to expose the source/drain region. A conductive layer is formed on the second insulation layer to fill the lower part of the opening and to cover a surface of the upper part of the opening. A spacer is formed on a part of the conductive layer on a side wall of the larger opening. A conductive spacer is formed on the spacer. The spacer is removed.

Abstract: The present invention relates to a process for preparing a wafer for chip packaging that minimizes stress and torque on wafer components during back grinding. The wafer has fabricated thereon a plurality of dies in a die side thereof opposite a back side thereof. A protective coating is spun on the die side to protect the dies. The wafer is separated into a plurality of connected pieces by scratching or cutting a recess into streets or scribe lines in the die side. The connected pieces of the wafer are secured to a surface with the back side thereof exposed. Material is removed from the back side of the wafer by chemical, mechanical, or chemical-mechanical methods until each piece is separated or disconnected from the other pieces. The protective coating is removed. The pieces can be situated upon a flexible surface that is stretched to increase the separation between pieces. Each die in the die side of each piece is then packaged into a die package.

Abstract: A thin film spiral inductor is formed on a ceramic or other suitable substrate in a manner which facilitates adjustment of the inductive value of the inductor after its fabrication on the substrate. The thin film inductor comprises a spiral conductive path having a plurality of conductive pads connected at different positions about the periphery of the spiral path. A conductive pad is also located at the center of the spiral path in electrical connection to the inner end of the path. The center pad and a selected one of the peripheral pads serve as terminals of the inductor to provide an intended value of inductance.

Abstract: The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the anti-reflection layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended sourcedrain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the anti-reflection layer is then removed. A second silicon layer is formed on the semiconductor substrate and the first silicon layer. Another doping step is performed to dope the substrate to form a source/drain junction in the substrate under a region uncovered by the gate region and the undoped spacer structure.