Abstract: A method of forming an anti-reflective coating material layer in the fabrication of integrated circuits includes providing a substrate assembly having a surface and providing an inorganic anti-reflective coating material layer on the substrate assembly surface. The inorganic anti-reflective coating material layer has an associated first etch rate when exposed to an etchant. The method further includes thermally treating the inorganic anti-reflective coating material layer formed thereon such that the thermally treated anti-reflective coating material layer then has an associated second etch rate less than the first etch rate when exposed to the etchant, e.g., the second etch rate is less than 16 Å/minute, the second etch rate is less than 20% of the first etch rate, etc.

Abstract: In order to form a first capacitor having a small capacitance and a second capacitor having a large capacitance on a substance with a minimum number of manufacturing steps, at least one of electrodes of the first capacitor and at least one of electrodes of the second capacitor are formed simultaneously.

Abstract: In the etching method, ozone water containing an oxidation agent having an oxidation-reduction potential of 2V or more is supplied onto a metal compound film such as SrRuO film or the like, and the metal compound film is etched by oxidation-reduction reaction involving oxygen. The metal compound film, which is conventionally removed by a physical removal method, can be easily removed by wet etching. Manufacture of a capacitor containing an SrRuO film and the like can thus be facilitated.

Abstract: A process to remove a semiconductor die from a plastic package and then to reassemble the die in a high reliability hermetic package. The process is used to remove an already existing die using a unique disassembly and etching process and make the removed die more reliable by reattaching the die and rebonding all new die wires into either a hermetic package or a different type of package with a “bond-on-top-of-bond” technique. The original bondfoot on the removed die may be first preconditioned by a novel bond-flattening tool, which can be attached to the bond-head chuck of any wirebonder. Also, the die can be used in other applications with different pin-outs or configurations.

Abstract: A method for fabricating FETs with abrupt halos provides an initial FET structure having a substrate, a dielectric layer over a portion of the substrate, a gate over the dielectric layer, sidewall insulators on either side of and adjacent the dielectric layer and gate, and halo regions comprising an n- or p-type dopant extending to a desired depth in the substrate adjacent each of the sidewall insulators and beneath a portion of the dielectric layer. The method is practiced by creating first amorphous regions within a portion of each of the halo regions to a depth less than the halo regions and implanting in and diffusing throughout only the first amorphous regions a dopant opposite the n- or p-type dopant used in the halo region to create extension source and drain regions. The method then involves forming dielectric spacers adjacent the sidewall insulators and creating second amorphous regions adjacent each of the dielectric spacers to a depth greater than the halo regions.

Abstract: A method of manufacturing copper wiring in a semiconductor device by forming a diffusion prevention film on a damascene pattern, forming a first copper film by a PVD method, forming a second copper film by a spin-on coating method, and forming a third copper film by a PVD or electrochemical deposition method. The method provides a good coverage characteristic and can prevent generation of voids etc., thus improving reliability of the device.

Abstract: A method of forming a semiconductor device assembly comprising forming a wire bump on at least one bond pad on the active surface of a semiconductor device and connecting one end of a wire to the wire bump using a wire bond. The wire bump may be flattened before connecting one end of a wire thereto.

Abstract: The pressure sensor is integrated in an SOI (Silicon-on-Insulator) substrate using the insulating layer as a sacrificial layer, which is partly removed by chemical etching to form the diaphragm. To fabricate the sensor, after forming the piezoresistive elements and the electronic components integrated in the same chip, trenches are formed in the upper wafer of the substrate and extending from the surface to the layer of insulating material; the layer of insulating material is chemically etched through the trenches to form an opening beneath the diaphragm; and a dielectric layer is deposited to outwardly close the trenches and the opening. Thus, the process is greatly simplified, and numerous packaging problems eliminated.

Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.

Abstract: A method of manufacturing integrated circuits having single and multiple device modes is described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a “by n” input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a “×n” configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a “×2n” configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: The present invention relates to a process for preparing a wafer for chip packaging that minimizes stress and torque on wafer components during back grinding. The wafer has fabricated thereon a plurality of dies in a die side thereof opposite a back side thereof. A protective coating is spun on the die side to protect the dies. The wafer is separated into a plurality of connected pieces by scratching or cutting a recess into streets or scribe lines in the die side. The connected pieces of the wafer are secured to a surface with the back side thereof exposed. Material is removed from the back side of the wafer by chemical, mechanical, or chemical-mechanical methods until each piece is separated or disconnected from the other pieces. The protective coating is removed. The pieces can be situated upon a flexible surface that is stretched to increase the separation between pieces. Each die in the die side of each piece is then packaged into a die package.

Abstract: The present invention discloses a method for forming an overlay vernier that can prevents deformation of the mother vernier. The method comprises the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.

Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.

Abstract: A switch includes a conductive region, a membrane, and a dielectric region. The dielectric region is formed from a dielectric material and is disposed between the membrane and the conductive region. When a sufficient voltage is applied between the conductive region and the membrane, a capacitive coupling between the membrane and the conductive region is effected. The dielectric material has a resistivity sufficiently low to inhibit charge accumulation in the dielectric region during operation of the switch.

Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

Abstract: A vertical double diffuses MOSFET includes a nitride film (26) formed on a gate electrode (18). An ion implant window (34) is formed through the nitride film. P-type ions are implanted through the ion implant window into the semiconductor substrate (12), and the implanted ions are diffused to thereby form a main diffusion region (14). At the same time, the oxide film is grown inside the ion implant window to form a thick walled portion (36). Ions of the p-type are implanted through, as a mask, the thick walled portion, gate electrode and nitride film into semiconductor substrate, and thermally diffused thus forming a channel diffusion region (22). Further, n-type ions are implanted through the same mask and then thermally diffused to provide source diffusion regions.

Abstract: In one implementation, a method of depositing a nitrogen enriched metal layer over a semiconductor substrate includes providing a sputter deposition reactor chamber having an inductive coil positioned therein, a metallic target position therein, and a semiconductor substrate positioned therein. A nitrogen containing source gas and a sputtering gas are fed to the reactor chamber. The reactor is operated to provide a selected target power, inductive coil power and substrate bias during the feeding effective to deposit an MNx comprising layer on the substrate, where “M” is an elemental metal and “x” is greater than 0 and less than 1. One implementation also includes forming a silicide contact to silicon from such layer, preferably with a silicon layer being formed over the MNx comprising layer.

Abstract: A method of making an active device is provided. A conductive line is formed in a substrate of a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET). The conductive line runs alongside a gate of the MOSFET. The gate is coupled to the conductive line.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: A method for fabricating a bit line junction in a DRAM array device which improves the doping profile in the channel region. The method includes contradoping via ion implantation through the bit line contact opening made in the device during processing. This particular doping method increases the concentration of dopants in the channel region on the bit line side of the array, without a corresponding increase of dopants on the buried strap side. Such a doping profile results in an improvement in the off current behavior of the device. Depending on the aspect ratio of the contact opening, tilt angles for the ion implantation are possible and can be adjusted for maximum off current efficiency.