Abstract: A traffic carrier waveform W.sub.n (.PHI.,R;t) being the product of a number of tones is employed in transmitting blocks of information from a transmit unit to a receive unit. The tones are geometrically increasing multiples of a frequency of a fundamental tone. Each tone incorporates a tone phase. The selection of these tone phases uniquely identifies each transmitted signal. The tone phases also is used as a `key` in converting a message signal into a direct wide spectrum signal for communication. To insure that third parties do not decode the transmitted message, the tone phases are transformed to seed phases by a method known to both the transmit and receive units, but not to third parties. The seed phases are then transmitted by intermittent preamble carrier waveform to the receive unit which transforms these into the tone phases and decodes the message signal. The seed phases may be dynamically changed according to a sequence known or generated by both the transmit unit and receive unit.

Abstract: A selective call receiving device (10) includes a signal decoder that utilizes both a peak and valley routine and a stochastic gradient feedback route for processing a received signal. The peak and valley routine is operable prior to the detection of a predetermined synchronization word in the received signal to detect the peak and valley of a received signal and to generated based on detected peak and valley, a DC offset correction value for correcting the received signal prior to symbol decoding. A number of threshold values are also generated based on the detected peak and valley of the signal for use by a symbol decoder (77). The symbol decoder (77) utilizes the threshold values for decoding a signal into symbols. The symbol decoder (77) also generates a feedback error that is used after the detection of the predetermined synchronization word for updating the DC correction value and for generating a gain correction value.

Abstract: The present invention provides a novel Geometric Harmonic Modulation (GHM) method. The GHM method functions in two modes, a preamble mode and a traffic mode. During the preamble mode, n+1 frequencies are each offset by a predetermined phase in a transmit unit and passed through a channel to a receive unit. The set of phases is used as the spreading code in the transmit unit, and also acts as an `address` of intended receive units. The receive unit monitors preamble signals to determine the phases. When it recognizes a set of phases, or `address`, which pertains to itself, the receive unit stores the phases and uses these phases to despread and decode the appended message. After the preamble mode is finished, the GHM modulator enters the traffic mode and requests the message to be transmitted from the message source. A traffic carrier waveform is created by multiplying tones, each having its specific phase. An analog or binary message is encoded by modulating the traffic carder waveform.

Abstract: A method of constructing a spreading code associated with one user of a direct sequence code division multiple access digital transmission system includes at least one stage of concatenating a plurality of different sub-codes. Specifically, the spreading code is constructed by concatenating at least two different, in particular, cyclically different, basic sub-codes belonging to the same family of basic sub-codes, and at least one secondary sub-code obtained by circular permutation of one of the basic sub-codes. The constructed spreading code is then designated as being associated with the one user.

Abstract: A clock signal or the power is constantly supplied to an interface board used in an active system. The power is supplied to a transmission line signal processing part, for processing a signal from a transmission line, of an interface board used in a reserve system at a predetermined cycle. The power is not supplied to a reserve transmission line of the interface board used in the reserve system.

Abstract: A computer peripheral is provided that combines the functionality of multiple devices, for example, a pager, a facsimile machine, and a data modem. The computer peripheral is designed as one or more separable modules, or functional components, including a module for interfacing the peripheral to a host computer. At least one of the functional components can be operated either as part of the computer peripheral, or may be separated from the remainder of the computer peripheral and used as a self contained functional module.

Abstract: In a direct sequence spread spectrum receiver, spread orthogonal data signals and spread orthogonal pilot signals are correlated with orthogonal despreading sequences at a chip rate. These despread signals are integrated at a symbol rate to produce orthogonal data symbols and orthogonal pilot symbols. A predetermined number of pilot symbols of each phase component are moving-averaged. Each phase component of the orthogonal data symbols is weighted with the moving average value of the corresponding phase component of the pilot symbols, and summed with the other weighted component of the data symbols to produce an output signal of the spread spectrum receiver.

Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), the primary site (102) and each of the secondary sites (104-108) includes a DMT receiver. Such a DMT receiver includes a discrete multi-tone decoder that receives a time domain discrete multi-tone symbol and produces an ordered data stream based on bit loading information and a data de-formatter, operably coupled to the discrete multi-tone decoder, wherein the data de-formatter receives the ordered data stream and produces a recovered data stream based on carrier channel allocation information.

Abstract: A spread spectrum modulating apparatus includes an oscillator outputting a carrier. A frequency multiplier multiplies a frequency of the carrier by a predetermined integer N1. A frequency divider divides the frequency of the carrier by a predetermined integer N2. A spread code generator uses an output signal of the frequency divider as a clock signal, and generates a spread code in response to the clock signal. A power supply feeds a dc bias voltage. An operation device executes a predetermined logic operation between the spread code and the dc bias voltage of the power supply. A switch selectively feeds an input information signal to either the oscillator or the point of connection of the power supply to the operation device, selecting between PSK and FSK as primary modulation. An output signal of the operation device and an output signal of the frequency multiplier are multiplied to execute a spectrum spreading process.

Abstract: An apparatus for variable-length-coding input symbols using a plurality of variable-length-code tables includes N variable-length-code tables each having a symbol-codeword association different from the others according to statistics regarding the symbols and a variable-length-coding device for coding the input symbols according to each of the variable-length-code tables for every block in a predetermined block data unit, for generating codewords, and for providing both table information representing each of the variable-length-code tables utilized in generating the respective codewords and a control signal indicating that variable-length-coding to a predetermined block data unit has been completed.

Abstract: A method of modem power conservation used in a data communications system having an infrastructure (101), and a modem (103), the modem registered with the infrastructure and adapted to provide data communications between a host terminal (105) and the infrastructure (101), the method including the steps of: receiving, at the modem (103), a message: determining that the message is not deliverable to the host terminal (105): and responsive thereto entering, at the modem (103), a power conservation mode. An alternative method directed to the same purposes includes the steps of: entering, at the modem (103), a power conservation mode after a first predetermined time has lapsed without message activity: exiting the power conservation mode after a second predetermined time has lapsed: and finally registering with the infrastructure (101).

Abstract: In a circuit for a demodulator of a radio data signal in a radio receiver, the multiplex signal in digital form is mixed into the baseband, in two phase positions shifted 90.degree. with respect to each other, after band-pass filtering, together with a reference carrier generated at a sampling clock rate produced in the radio receiver, thus producing a first and a second mix signal. A first and a second auxiliary signal with, respectively, a sine waveform and a cosine waveform are produced. The first mix signal is multiplied by the first auxiliary signal, and the second mix signal by the second auxiliary signal. The results of these multiplications are added together, producing a first output signal. The first mix signal is multiplied by the second auxiliary signal, and the second mix signal by the first auxiliary signal, and the results subtracted from each other, thus producing a second output signal.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: A hybrid type of decision feedback equalizer (DFE) structure that approaches optimal DFE performance is described. The hybrid DFE includes both an intersymbol interference DFE (ISI-DFE) and a noise predictive DFE (NP-DFE). The hybrid DFE structure is designed so that one form of tap values dominates over the other. This allows only the dominate tap values to be used by the transmitter during precoding and reduces the transmitter complexity. In particular, a hybrid DFE is designed so that the I(z) coefficient values dominate over the N(z) coefficient values, where the notation I(z) and N(z), as known in the art, represent the resulting coefficient values after adaptation of the ISI-DFE and the NP-DFE, respectively. A respective Tomlinson precoding scheme in the transmitter uses only the I(z) values. Since only the I(z) values are used in the precoder of the transmitter, the NP-DFE of the receiver is kept active during the communications phase.

Abstract: A clock synchronization control check system for a digital baseband signal receiver which digitally provides a phase error to digital data generated by a digital modulator without the need for conversion of the digital data to analog data so that clock synchronization control in its demodulating section can be checked easily and precisely. In the system, a digital filter is used to suppress inter-symbol interference, and a set of filter coefficients for the digital filter is shifted along the time axis of an impulse response so as to provide a plurality of filter coefficient sets. By selecting one of the coefficient sets, a desired phase shift is given to the digital data signal.

Abstract: An adaptive circuit is used in the process of recovering data from a signal received from a communications channel. This circuit scripts or varies its transfer function in response to a first error signal derived from the received signal. This adaptation results in the device's transfer function settling to a converged state. An auxiliary information recovery circuit receives the recovered data and derives auxiliary information therefrom. To avoid the problem of false state convergence, the auxiliary information circuit provides a second error signal which causes the adaptive device to reinitiate the adaptation process. In the disclosed embodiment, the adaptive circuit is an equalizer and the auxiliary information recovery circuit is one which recovers framing information or is an error correction circuit. The inability of the auxiliary information circuit to function properly is used as an indication of false convergence of the adaptive circuit.

Abstract: A radio receiver apparatus receives a transmission signal having a reference pattern formed of a predetermined bit pattern. The apparatus has a receiving unit, a received data processing unit and first and second phase shift information detection units. The receiving unit demodulates the transmission signal to generate received data. The received data processing unit processes the received data in synchronism with the reference pattern. The first phase shift information detection unit detects first phase shift information of the received data corresponding to the data processing of the received data processing unit. The second phase shift information detection unit shifts the phase of the received data so as to detect second phase shift information of the received data corresponding to the data processing of the data processing unit. The apparatus corrects the phase shift of the received data by comparing output signals from the first and second phase shift detection units.

Abstract: Apparatus for rapidly acquiring a high performance gain long PN code having a preamble header in real time includes appratus for rapid acquiring and tracking a short PN code in said preamble header and further includes apparatus for demodulating and tracking a long PN code which follows said preamble header. After acquiring the short PN code, the short PN replica code is applied to the long code demodulation and tracking apparatus. The short PN code is employed to synchronize the long code demodulation and tracking apparatus by detecting the time of occurrence of a sync word in said preamble header and is employed to generate a switch point signal and switch from a short PN replica code to a long PN replica code at the input to the long code demodulation and tracking device in real time.

Abstract: A serial data transfer apparatus is provided with a counter 7 for counting the frequency clocks DCLK as the number of clocks of the transfer clocks TCLK, a decoder 8 for detecting the count value CV1 of the counter 7, a transfer interval timer 9 for counting a transfer interval, and with a control circuit 10, wherein the transfer interval timer 9 is made to start counting the frequency clocks DCLK at the time of the last transfer clocks TCLK, i.e., a value of one count before the last count of the counter 7 is detected by the decoder 8. When the transfer interval timer 9 has finished its counting of clock pulses, the control circuit 10 makes the counter 7 start counting the frequency dividing clocks DCLK as well as making the transfer clock output circuit 11 output the next transfer clock TCLK.

Abstract: A signal processing unit selects signal components included in the frequency bands of respective channels from a burst signal input from a terminal, and outputs the selected signal components to a memory after they are converted into digital data. A frequency switching unit sequentially switches the frequency bands at a predetermined time interval in correspondence with the respective channels. A data write unit stores the digital data in the memory for every channel in response to switching of the frequency bands. A data read-out unit reads out data from the memory, specifies the timing of the burst signal, and reads out necessary data for every channel on the basis of the specified timing. A power arithmetic operation unit calculates electric power of each channel based on the readout data, thus obtaining the adjacent and alternate channels power.