Abstract: A system for recovering parameters of an underlying clock signal from data modulated signals includes a time digitizer, or time stamping device, for sampling and locating edges of the data modulated signals, thereby selectively providing time stamp readings identifying incoming edges of the data signals. The time stamp readings are used, along with a user-input nominal clock frequency, to determine an array of actual clock cycle stamps, each representing an integral number of actual clock cycles occurring between adjacent time stamps. The array is then used in conjunction with the time stamps to characterize parameters of the underlying clock data. Once the clock parameters are recovered, a wide variety of information, for example, frequency and phase information, including jitter, can be determined with a very modest rate of sampling compared to the high data bandwidth. No phase locked loops are used and no physical clock is recovered.

Abstract: A bidirectional data transceiver circuit is described which automatically transfers data from a first bidirectional data port to a second bidirectional data port when new data is detected. The transceiver has a collision arbitration circuit which prevents the device from driving data onto a data port that is being driven externally. An additional embodiment is described wherein the transition detection circuitry of the transceiver is used to provide a input transition detection flag for an integrated circuit having standby or low power modes. An integrated circuit providing an array of the transceivers of the invention is described. A transceiver which automatically detects a transition in data and provides output drive for data busses is described. Other devices, systems and methods are also described.

Abstract: An apparatus for snubbing or blanking digital signals representing a band of signals that includes an encoded carrier signal transmitted over a power line. An average signal level is compared with the instantaneous signal level to develop a blanking circuit control signal. Additionally, snubbing occurs in the circuit which determines the average signal level to prevent noise from building-up the average signal level. A hold-off signal is used in this circuit to prevent the average signal level from being latched permanently low. A unique infinite impulse filter subtracts out the D.C. offset thereby improving the dynamic range of the blanking. Additionally, the average signal level is used by AGC logic to control the gain at the front end of the apparatus. The state and switching of the AGC is controlled to minimize errors.

Abstract: A desynchronizer (10) for eliminating output mapping jitter includes a demapper circuit (12) for reading asynchronous data and a clock rate of an embedded signal within a synchronous channel (14). Payload data from the embedded signal is buffered within an elastic store circuit (17). The demapper circuit (12) outputs bit stuff and pointer justification timing adjustments to an overhead gapfill circuit (19) and a pointer justification leaky accumulator circuit (20). The overhead gapfill circuit (19) calculates overhead gaps within the payload data in order to generate a gapfill value (34). The pointer justification leaky accumulator circuit (20) determines the bit stuffs and pointer justifications occurring in the payload data in order to produce an accumulated value (36).

Abstract: Detection of a digitally modulated radio signal whose underlying data contain repetition structures is achieved by generating a binary spectrum from the frequency domain spectral amplitudes. The binary spectrum of the signal can be rastered at the signal's framing rate or other periodicity to create a two dimensional matrix with the set periodic bits falling along column of the matrix. Application of non-linear logical filtering operations removes speckle caused by aperiodic bits while maintaining the run of aligned periodic bits along the column of the matrix. To automate the line detection process, statistical values and measured line lengths in the binary matrix are used to adjust processing parameter values.

Abstract: A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).