Patents Examined by Jeffrey Zweizig
  • Patent number: 10158351
    Abstract: According to one or more embodiments, a skew control circuit for controlling the skew between at least two digital signals is provided. The skew control circuit may include a pulse generator that may generate a pulse with a pulse width, whereby the pulse width of the pulse may depend on a skew between edges of the two digital signals. The skew control circuit may also include a pulse width sensor that may output a pulse width value that represents the pulse width of the generated pulse. The skew control circuit may further include a skew controller that may adjust a delay of the at least one of the digital signals based on a target skew value and the pulse width value.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10156864
    Abstract: In accordance with an embodiment, an integrated circuit includes a substrate, an amplifier MOSFET, and a bias voltage terminal configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 18, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Winfried Bakalski, Werner Simbuerger, Anton Steltenpohl, Hans Taddiken
  • Patent number: 10157894
    Abstract: A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and having a third via and a fourth via through the second chip. The first chip includes: a first logical operation circuit configured to perform a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via; a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaru Koyanagi
  • Patent number: 10148132
    Abstract: Aspects of return coupled wireless power transmission systems are described. In one embodiment, a system includes a guided surface waveguide probe including a charge terminal elevated at a height over a lossy conducting medium, and a feed network. The system further includes a conductor coupled to the guided surface waveguide probe that extends a distance away from the guided surface waveguide probe across the lossy conducting medium, and at least one guided surface wave receivers coupled to the conductor. The conductor can help to provide additional efficiency in power transfer between the guided surface waveguide probe and the guided surface wave receivers, especially when the operating frequency of the probe is in the medium, high, or very high frequency ranges.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 4, 2018
    Assignee: CPG Technologies, LLC
    Inventors: James F. Corum, Kenneth L. Corum
  • Patent number: 10135434
    Abstract: Disclosed is an electronic circuit for controlling a half H bridge, the half split H bridge including first and second MOSFET transistors of different respective types, with sources connected respectively to a supply line and to an electric mass, and with respective drains connected to a load. Moreover, the control circuit includes first and second bipolar transistors of different respective types, with collectors connected to the supply line and to the electric mass, respectively, and with respective bases connected to a control module for controlling the MOSFET transistors, as well as first and second arms mounted parallel relative to one another between the gates of the MOSFET transistors, connected to the emitter of the first bipolar transistor and of the second bipolar transistor, respectively, the first arm including a first diode and a first resistor, and the second arm including a second diode and a second resistor.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: November 20, 2018
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Julien Mouret, Christian Pradelles
  • Patent number: 10135444
    Abstract: The booster precharges a boost-voltage-output terminal to a predetermined voltage before voltage-boosting start by a charge-pump circuit in the booster. While alternately switching one capacitive electrode of a pumping capacitance between first and second voltages, the charge-pump circuit periodically applies a third voltage to the other capacitive electrode, in which the voltage is boosted by lifting up the third voltage each switching. The resultant boost voltage is successively supplied to a stabilization capacitance through a MOS switch circuit for output. Thus, a boost voltage boosted to a sum voltage of the second and third voltages can be obtained. Using a precharge voltage produced by the precharge circuit in the booster as the third voltage can make a MOS switch circuit operable to supply the third voltage and the MOS switch circuit for boost voltage output smaller than a voltage under the sum voltage of the second and third voltages.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 20, 2018
    Assignee: Synaptics Japan GK
    Inventor: Yutaka Saeki
  • Patent number: 10133299
    Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a sinusoidal clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and arranged as a standing wave resonator. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line is conductively coupled to an associated circuit and has a plurality of inductive couplings to the at least one resonator rib to inductively generate a clock current corresponding to the sinusoidal clock signal via each of the plurality of inductive couplings in an additive manner to provide functions for the associated circuit.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 20, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Joshua A. Strong, Max Earl Nielsen
  • Patent number: 10135298
    Abstract: Disclosed herein are various embodiments for a guided surface waveguide probe and a guided surface wave receiver, where the guided surface wave receiver comprises processing circuitry that (a) identifies at least one frequency from a plurality of available frequencies associated with a transmission of Zenneck surface waves along a terrestrial medium, and (b) adjusts a frequency at which the guided surface wave receiver receives electrical energy from the Zenneck surface waves via the terrestrial medium to a predetermined frequency.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 20, 2018
    Assignee: CPG Technologies, LLC
    Inventors: James F. Corum, Kenneth L. Corum
  • Patent number: 10132845
    Abstract: Disclosed are various approaches for measuring and reporting the amount of electrical power consumed by an electrical load attached to a guided surface wave receive structure. A guided surface wave receive structure is configured to obtain electrical energy from a guided surface wave traveling along a terrestrial medium. An electrical load is coupled to the guided surface wave receive structure, the electrical load being experienced as a load at an excitation source coupled to a guided surface waveguide probe generating the guided surface wave. An electric power meter coupled to the electrical load and configured to measure the electrical load.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 20, 2018
    Assignee: CPG TECHNOLOGIES, LLC
    Inventors: James F. Corum, Kenneth L. Corum, Joseph F. Pinzone, James D. Lilly, Michael W. Miller, Stephen W. Wilson
  • Patent number: 10115743
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Patent number: 10110060
    Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoki Yasukawa, Akira Oizumi, Toyohiko Yoshida, Yoshinori Tokioka
  • Patent number: 10108071
    Abstract: A technique relates to a circuit for a sum frequency generator. A first resonator is connected to a Josephson ring modulator (JRM), and the first resonator is configured to receive a first photon at a first frequency. A second resonator is connected to the JRM, and the second resonator is configured to have a first harmonic and no second harmonic. The second resonator is configured to receive a second photon at a second frequency, and the first resonator is configured to output an up-converted photon. The up-converted photon has an up-converted frequency that is a sum of the first frequency and the second frequency.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10103723
    Abstract: In a driving apparatus for switches connected in parallel to each other, drivers respectively turn on or off the switches. A temperature obtainer obtains a value of a temperature parameter correlating with a temperature of at least one of the first and second switches. A selector selects at least one of the switches as at least one drive target switch. A driver causes at least one of the drivers to turn on the at least one drive target switch during an on duration and thereafter turn off the at least one drive target switch in each target switching cycle. The selector adjusts the number of the selected at least one drive target switch based on the value of the temperature parameter.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: October 16, 2018
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Shimizu, Kengo Mochiki, Yuu Yamahira, Tetsuya Matsuoka, Kazuma Fukushima, Mitsunori Kimura, Yasuyuki Ohkouchi
  • Patent number: 10090838
    Abstract: An apparatus includes an integrated circuit, which includes a processor core, a plurality of input/output (I/O) circuits, and a plurality of over voltage tolerant (OVT) circuits. Each I/O circuit is associated with an I/O pad and is associated with an OVT circuit of the plurality of OVT circuits. At least one of the OVT circuits includes a passive circuit, which is adapted to receive a pad voltage from the associated I/O pad; receive a supply voltage of the associated I/O circuit; and based on a relationship of the received pad voltage relative to the received supply voltage, selectively couple a gate of a transistor of the associated I/O circuit to the pad voltage to inhibit a leakage current.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 2, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Chao Yang, Matthew Powell
  • Patent number: 10090758
    Abstract: Embodiments herein provide electronic devices that include a charge pump coupled to a split reservoir capacitor which includes at least two discrete capacitors. Further, the discrete capacitors are coupled together by a switch (e.g., a transistor) which is controlled by an output regulator. In one embodiment, the output regulator monitors an output voltage of the charge pump and the split reservoir capacitor to determine when the output differs from a predetermined target voltage. When the switch isolates the two capacitors, the charge pump can continue to add charge to a first one of the discrete capacitors. Thus, when the output regulator detects a dip in the output voltage and activates the switch to reconnect the two discrete capacitors, the first discrete capacitor has extra charge which can decrease the time needed to bring the output voltage back to the target voltage.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 2, 2018
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Zheming Li, Chunbo Liu, Steve Chikin Lo
  • Patent number: 10090759
    Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Qiang Tang
  • Patent number: 10084442
    Abstract: A semiconductor device according to an embodiment includes a normally-off transistor having a first source, a first drain, and a first gate; a normally-on transistor having a second source electrically connected to the first drain, a second drain, and a second gate, a capacitor having a first end and a second end, the second end being electrically connected to the second gate, a first diode having a first anode electrically connected between the second end and the second gate and having a first cathode electrically connected to the second source, a first resistor provided between the first end and the first gate, and a second diode having a second anode electrically connected to the first end and having a second cathode electrically connected to the first gate, the second diode being provided in parallel with the first resistor.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Ikeda, Takenori Yasuzumi, Kohei Hasegawa
  • Patent number: 10084374
    Abstract: According to embodiments, a semiconductor device includes a first switching element in which a first reference voltage is input to a gate; a second switching element in which a first voltage is input to a gate; a third switching element to which the first switching element is in Darlington connection; a fourth switching element to which the second switching element is in Darlington connection; a first current mirror circuit to regulate currents flowing in the third and fourth switching elements; a fifth switching element switched between ON and OFF states based on a difference between the first reference and the first voltages; a constant current circuit; a second current mirror circuit; and a voltage setting resistance element between a source of the first switching element and a gate of the third switching element or between a source of the second switching element and a gate of the fourth switching element.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Chisaka, Kei Kasai
  • Patent number: 10084432
    Abstract: A semiconductor device according to an embodiment includes; an N-channel type first MOS transistor having a first drain connected to an input terminal, a first source connected to an output terminal, a first gate insulation film, and a first gate; a P-channel type second MOS transistor having a second drain connected to the input terminal in parallel with the first drain, a second source connected to the output terminal in parallel with the first source, a second gate insulation film whose area is larger than an area of the first gate insulation film, and a second gate; an inverter connected to a control terminal in parallel with the first gate; and a delay circuit disposed between the inverter and second gate.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hironori Nagasawa
  • Patent number: 10075145
    Abstract: Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 11, 2018
    Assignee: The Regents of the University of California
    Inventor: Qun Gu