Patents Examined by Jeremy Norris
  • Patent number: 9451693
    Abstract: A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 20, 2016
    Inventors: Rabindra N. Das, Voya R. Markovich, John M. Lauffer, Roy H. Magnuson, Konstantinos I. Papathomas, Benson Chan
  • Patent number: 8729406
    Abstract: Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a bump pad formed in the insulating member so as to be connected to the circuit pattern and protruding from an outer surface of the insulating member, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 20, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventor: Young Gwan Ko
  • Patent number: 8710375
    Abstract: The present invention provides a display device substrate that enables microfabrication of lines and is capable of reducing faulty connection and enhancing the reliability of display devices including the display device substrate, a method for producing the display device substrate, a display device, a method for forming a multilayer wiring structure, and a multilayer wiring board. The display substrate of the present invention includes an insulating substrate and includes at least one of a terminal area having a connection terminal to be connected to an external connection component and a peripheral circuit region having a peripheral circuit formed thereon, on the insulating substrate. The display device substrate includes an organic insulating film and an inorganic insulating film, and the inorganic insulating film is stacked directly on and above the organic insulating film such that an organic-inorganic film stacked body is formed.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: April 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroyuki Moriwaki
  • Patent number: 8711570
    Abstract: Flexible circuits for routing signals of a device, such as a touch sensor panel of a touch sensitive device, are provided. The flexible circuit can include a first set of traces for routing a first set of lines and a second set of traces for routing a second set of lines. The first set of traces can couple together the ends of at least a portion of the first set of lines. Additionally, the first set of traces can be non-intersecting or non-overlapping with the second set of traces. The flexible circuit can have a T-shape configuration and can be incorporated within a touch sensitive device, display device, printed circuit board, or the like. The flexible circuit can be placed over another flexible circuit, and can extend onto the device.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Apple Inc.
    Inventors: Steven Porter Hotelling, Joshua G. Wurzel, Steven J. Martisauskas, Thayne M. Miller, Kuo-Hua Sung
  • Patent number: 8704102
    Abstract: A twisted-pair cable and methods are disclosed. The twisted-pair cable comprises a first layer comprising a first non-conductive. A second layer is coupled to the first layer, and comprises a printed circuit patterned with first diagonal conductor segments. A third layer is coupled to the second layer, and comprises a non-conductive strip. A fourth layer is coupled to the third layer, and comprises a printed circuit patterned with second diagonal conductor segments. The first diagonal conductor segments and the second diagonal conductor segments are coupled at respective segment ends such that at least two wires are formed around the non-conductive strip. A fifth layer is coupled to the fourth layer, and comprises a second non-conductive.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 22, 2014
    Assignee: The Boeing Company
    Inventors: Jeffrey L. Duce, Joseph A. Marshall
  • Patent number: 8704368
    Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<½×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 22, 2014
    Inventors: Akito Yoshida, Mahmoud Dreiza, Curtis Michael Zwenger
  • Patent number: 8704105
    Abstract: A composition for forming transition vias and transition line conductors is disclosed for minimizing interface effects at electrical connections between dissimilar metal compositions. The composition has (a) inorganic components selected from the group consisting of (i) 20-45 wt % gold and 80-55 wt % silver and (ii) 100 wt % silver-gold solid solution alloys, and (b) an organic medium. The composition may also contain (c) 1-5 wt %, based upon the weight of the composition, of oxides or mixed oxides of metals selected from the group consisting of Cu, Co, Mg and Al and/or high viscosity glasses mainly containing refractory oxides. The composition may be used as a multi-layer composition in a via fill. Multi-layer circuits such as LTCC circuits and devices may also be formed using the composition for forming transition vias and transition line conductors.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 22, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Kumaran Manikantan Nair, Scott E Gordon, Mark Frederick McCombs
  • Patent number: 8699233
    Abstract: Manufacturing method and circuit module, which comprises an insulator layer (1) and, inside the insulator layer (1), at least one component (6), which comprises contact areas (7), the material of which contains a first metal. On the surface of the insulator layer (1) are conductors (22), which comprise at least a first layer (12) and a second layer (32), in such a way that at least the second layer (32) contains a second metal. The circuit module comprises contact elements between the contact areas (7) and the conductors (22) for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area (7), an intermediate layer (2), which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer (2) and the contact area (7) is less that the surface area (APAD) of the contact area (7).
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: April 15, 2014
    Assignee: GE Embedded Electronics Oy
    Inventors: Petteri Palm, Risto Tuominen, Antti Iihola
  • Patent number: 8698008
    Abstract: A packaging substrate is provided, which includes: a core layer having opposite first and second surfaces; two circuit layers formed on the first and second surfaces, respectively; a plurality of conductive through holes penetrating the core layer and electrically connected to the first and second circuit layers; two insulating protection layers disposed on the first and second surfaces of the core layer and the circuit layers; and a carrier attached to one of the insulating protection layers for preventing cracking of the packaging substrate during transportation or packaging.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 15, 2014
    Assignee: Advance Materials Corporation
    Inventors: Lee-Sheng Yen, Doau-Tzu Wang
  • Patent number: 8692136
    Abstract: There are provided a method of repairing a probe card and a repaired probe board. The method of repairing a probe card includes: in a board body composed of a sintered ceramic having first and second pillar surfaces disposed at a position opposed to each other, preparing the board body including a plurality of main channels for electrically connecting a first pad formed on the first pillar surface to a second pad formed on a second pillar surface and reserved channels disposed to be adjacent to the main channels to repair to damaged main channels; when the main channels are damaged; removing the first and second pads formed in the main channels and the reserved channels; forming cavities by partially removing the board between the damaged main channels and the reserved channels adjacent to the main channel; and forming repair connection parts in the cavities in order to electrically connect the damaged main channels to the reserved channels adjacent thereto.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: April 8, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Jae Oh, Joo Yong Kim, Yoon Hyuck Choi, Bong Gyun Kim
  • Patent number: 8692790
    Abstract: A capacitive touch sensitive housing comprises: a housing wall; an array of capacitive touch sensor pads formed on the housing wall; a plurality of conductive bonding pads formed on the housing wall; and a plurality of conductive lines formed on the housing wall. Each conductive line extends from a respective one of the touch sensor pads to a respective one of the bonding pads and cooperates with the respective one of the capacitive touch sensor pads and the respective one of the bonding pads to define a touch sensor unit having a layered structure including an active metal layer and an electroless deposited metal layer. The active metal layer contains an active metal capable of initiating electroless deposition.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Sheng-Hung Yi, Pen-Yi Liao
  • Patent number: 8692125
    Abstract: A multilayer substrate that retains a curved state without causing fluctuations in electrical characteristics includes a main body including a plurality of insulating sheets to be stacked and made of a flexible material. A signal wire extends in the main body. A ground conductor is provided at a positive-direction side in a z-axis direction relative to the signal wire in the main body, and overlaps the signal line in a plan view seen from the z-axis direction. A ground conductor is provided on a negative-direction side in the z-axis direction relative to the signal wire in the main body, and overlaps the signal line in a plan view seen from the z-axis direction. The state in which the main body is curved so that the signal wire defines an arc is retained by plastic deformation of the ground conductors.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: April 8, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Jun Sasaki, Satoshi Ishino
  • Patent number: 8693211
    Abstract: A wiring substrate 11 includes a wiring substrate main body 31 having a semiconductor element mounting area A, a wiring pattern 33 provided on an upper surface 31A of the wiring substrate main body 31 at a portion corresponding to the semiconductor element mounting area A, a solder resist 35 provided on the upper surface 31A of the wiring substrate main body 31 and having an opening portion 43 whose size is substantially equal to the semiconductor element mounting area A when viewed from a top, and a dam 37 provided on the solder resist 35 to block an underfill resin 13 provided in a clearance between the semiconductor element 12 and the wiring substrate main body 31. A distance between an inner wall of the opening portion 43 of the solder resist 35 and an inner wall of the dam 37 is partially varied.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: April 8, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yuka Tamadate
  • Patent number: 8686296
    Abstract: An exemplary heat dissipation device includes a bracket, and heat sink and a pressing member. The bracket includes a bottom plate. An opening is defined in the bottom plate. Two supporting portions are formed from an underside of the bottom plate. The heat sink extends through the opening of the bracket, with bottom edges of the heat sink rested on the supporting portions. The pressing member is mounted on the bracket and elastically presses the heat sink onto the supporting portions.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 1, 2014
    Assignee: Foxconn Technology Co., Ltd.
    Inventors: Ching-Bai Hwang, Jui-Wen Hung
  • Patent number: 8687378
    Abstract: A high-frequency module includes first and second switch IC elements and a substrate. The first and second switch IC elements are the same or substantially the same IC chips, and are mounted in the same or substantially the same orientation. The first switch IC element is mounted on the substrate. The second switch IC element is mounted above the first switch IC element. Due to wire bonding, the individual pad electrodes of the first and second switch IC elements are connected to the land electrodes of the substrate, which are to be connected to the individual pad electrodes. Between a pad electrode and a land electrode connected to each other, another land electrode is not provided.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 1, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Nobuyoshi Okuda, Masaaki Kanae, Naoki Hayasaka
  • Patent number: 8686299
    Abstract: An electronic element unit (1) includes an electronic element (2) having a plurality of connecting terminals (12) on a lower surface thereof, a circuit board (3) having a plurality of electrodes (22) corresponding to the connecting terminals (12) on an upper surface thereof. The connecting terminals (12) and the electrodes (22) are connected by solder bumps (23), and the electronic element (2) and the circuit board (3) are partly bond by a resin bond part (24) made of a thermosetting material of a thermosetting resin, and a metal powder (25) is included in the resin bond parts (24) in a dispersed state. The metal powder (25) has a melting point lower than a temperature at which the resin bond parts (24) are heated when a work (a repairing work) is carried out for removing the electronic element (2) from the circuit board (3).
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
  • Patent number: 8671564
    Abstract: Disclosed is a substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: March 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hueng Jae Oh, Tae Joon Chung, Dong Gyu Lee, Seon Jae Mun, Jin Won Choi
  • Patent number: 8674233
    Abstract: A photosensitive conductive film 10 according to the invention includes a support film 1, a conductive layer 2 containing conductive fiber formed on the support film 1, and a photosensitive resin layer 3 formed on the conductive layer 2.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 18, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventor: Hiroshi Yamazaki
  • Patent number: 8665603
    Abstract: A housing for electrical components is provided. The housing may include a mouth portion to cooperate with a circuit board in an assembled condition wherein said circuit board is applied against said mouth portion of the housing. The housing may include at least one spring formation located at said mouth portion to cooperate with said circuit board to elastically urge said circuit board away from said mouth portion, and at least one hook-like formation extending from said mouth portion distally of said housing, said hook-like formation adapted to cooperate with said circuit board to retain said circuit board assembled to said housing against the force exerted by said spring formation.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: March 4, 2014
    Assignee: Osram Gesellschaft mit Beschraenkter Haftung
    Inventors: Alessandro Brieda, Giovanni Scilla, Alessandro Scordino
  • Patent number: 8664539
    Abstract: Implementations of encapsulated nanowires are disclosed.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: March 4, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick