Patents Examined by Jeremy Norris
  • Patent number: 8611105
    Abstract: A slide button, used for activating a mode of an electronic device by operating a toggle switch on a circuit board of the electronic device, includes an operating member, an activating member, and a positioning member. The operating member defines a first surface used for applying a force therein and a second surface opposite to the first surface. The activating member includes two tail fins and a positioning member respectively extending from the second surface. The tail fin defines an opening. The toggle switch is received in the opening. The connecting board is received in the opening and used for enhancing the strength of the two tail fins. The positioning member is connected to the two tail fins and spaced apart from the operating member. The positioning member and the operating member together secure the slide button to the electronic device.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: December 17, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd, Hon Hai Precision Industry Co., Ltd.
    Inventors: Wei Liu, Min-Li Li, Na Wang, Bao-Gang Zhao
  • Patent number: 8604346
    Abstract: Provided are a flex-rigid wiring board having an increased shielding effect and improved productivity with reduced number of manufacturing process steps, and a method for manufacturing the flex-rigid wiring board. The flex-rigid wiring board consists of a flexible cable section (32) having a shielding layer (45) on an outer surface, and a rigid mounting section (34) having a wiring layer (47) provided on the same surface as the shielding layer (45). The shielding layer (45) and the wiring layer (47) are made of a same sheet of continuous copper foil (46). The wiring layer (47) is plated and is made thicker than the shielding layer (45). A same continuous insulating layer (48) is provided on outer sides of the shielding layer (45) and the wiring layer (47) of the mounting section (34).
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: December 10, 2013
    Assignee: Sony Corporation
    Inventor: Atsuhiro Uratsuji
  • Patent number: 8604356
    Abstract: Various embodiments of an electronic assembly with increased standoff height are provided. In one exemplary embodiment, a substrate is provided. A metallic interconnection land is disposed over the substrate. A solder resist material is applied on a predefined portion of the metallic interconnection land. A metallic solder material is disposed over at least a portion of the solder resist material and contacts a surface of the metallic interconnection land. An air pocket is formed within the metallic solder material over at least a portion of solder resist material. The air pocket acts as a lifting mechanism to increase a standoff height between the substrate and a surface mount component.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: December 10, 2013
    Assignee: Amkor Technology, Inc.
    Inventor: Victor Carl Kessler
  • Patent number: 8604352
    Abstract: Semiconductor chip mounting yield and semiconductor package reliability deteriorate due to warpage of a multilayer circuit board. A multilayer circuit board (1) using an interlayer insulating layer (6) can suppress warpage of the entire multilayer circuit board (1) by making the interlayer insulating layer (6) serve as a buffer material. In the multilayer circuit board (1) using the interlayer insulating layer (6), conductor circuit layers (11) and interlayer insulating layers (6) are alternately arranged. The interlayer insulating layer (6) to be used in the multilayer circuit board (1) includes a first insulating layer and a second insulating layer having an elastic modulus higher than that of the first insulating layer.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: December 10, 2013
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventors: Hironori Maruyama, Hitoshi Kawaguchi, Hiroyuki Tanaka
  • Patent number: 8604348
    Abstract: A packaged microelectronic element includes connection component incorporating a dielectric layer (22) carrying traces (58) remote from an outer surface (26), posts (48) extending from the traces and projecting beyond the outer surface of the dielectric, and pads (30) exposed at the outer surface of the dielectric layer, the pads being connected to the posts by the traces. The dielectric element overlies the front surface of a microelectronic element, and contacts (74) exposed on the front surface of the microelectronic element are connected to the pads by elongated leads (76) such as wire bonds. Methods of making the connection component are also disclosed.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: December 10, 2013
    Assignee: Tessera, Inc.
    Inventors: Yoichi Kubota, Teck-Gyu Kang, Jae M. Park, Belgacem Haba
  • Patent number: 8604351
    Abstract: A printed circuit board includes a signal layer and a reference layer. The signal layer is covered with copper foil. A circuit topology for multiple loads is set on the signal layer. The circuit topology includes a driving terminal, a first signal receiving terminal, and a second signal receiving terminal. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals respectively through a second and a third transmission lines. A difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. The reference layer is covered with copper foil, and arranged under the signal layer. A region without copper foil is formed on the reference layer, under the second transmission line.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 10, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Hua-Li Zhou, Chia-Nan Pai, Shou-Kuo Hsu
  • Patent number: 8604349
    Abstract: A multilayer substrate includes a plurality of stacked thermoplastic resin layers each including an in-plane conductive pattern provided on one principal surface thereof and an interlayer conductive portion arranged to penetrate through the thermoplastic resin layer in a thickness direction. The plurality of thermoplastic resin layers include a first thermoplastic resin layer and a second thermoplastic resin layer, a stacking direction of which is inverted with respect to a stacking direction of the first thermoplastic resin layer. The second thermoplastic resin layer is thicker than the first thermoplastic resin layer. One end in the thickness direction of the interlayer conductive portion provided in the second thermoplastic resin layer is connected with the interlayer conductive portion of the thermoplastic resin layer adjacent to the second thermoplastic resin layer in the thickness direction such that the in-plane conductive pattern is not interposed therebetween.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: December 10, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Norio Sakai
  • Patent number: 8598467
    Abstract: A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 3, 2013
    Assignee: PPG Industries Chio, Inc.
    Inventors: Kevin C. Olson, Alan G. Wang
  • Patent number: 8595922
    Abstract: The embodiments disclose a method for creating a silicone encased flexible cable using manufacturing machinery including arranging plural individual conduits, at least one assembly and at least one junction box assembly into a grouped arrangement including at least one of the conduits is a fluid communication conduit, wherein the silicone encased flexible cable is coupled between a controller and an electro-mechanical device, and wherein the fluid communication conduit is configured to transfer at least a liquid and pneumatic gas through the silicone encased flexible cable during operation of the electro-mechanical device; and integrating a snap washer within the singular encasement, wherein the manufacturing machinery is configured to cut a slit along the cable run of a silicone encased flexible cable, insert a snap washer base through the slit and position a snap washer into the snap washer and snapping the snap washer into a locked position.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 3, 2013
    Inventors: Howard Lind, John Palahnuk
  • Patent number: 8598466
    Abstract: A shielded signal pass-through or via structure integral with an electronic circuit board is described. The structure includes a rigid inner generally cylindrical conductor; at least a semi-rigid intermediate annular dielectric surrounding the conductor; and a rigid outer annular conductor surrounding the dielectric material. Also described is an interconnect device that presents a contact array in a boss region of a unitary embossed printed circuit board (PCB) optionally equipped with one or more such shielded vias.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: December 3, 2013
    Assignee: Tektronix, Inc.
    Inventors: Brian S. Mantel, David T. Engquist
  • Patent number: 8598461
    Abstract: The embodiments disclose a silicone encased flexible cable comprising plural individual conduits and at least one junction box configured into a grouped arrangement including at least one of the conduits is a fluid communication conduit for transferring fluid through the cable, wherein the silicone encased flexible cable is coupled between a controller and an electro-mechanical device, and wherein the fluid communication conduit is configured to transfer at least a liquid and pneumatic gas through the silicone encased flexible cable during operation of the electro-mechanical device; and a mixture of silicone and additives, wherein the additives include graphite and conductive materials mixed within the grouped arrangement, wherein the mixture of silicone and additives is used to create a curved ā€œUā€ shaped self supporting portion surrounding the grouped arrangement during manufacturing as a singular encasement that is capable of sustaining its shape.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 3, 2013
    Inventors: Howard Lind, John Palahnuk
  • Patent number: 8593824
    Abstract: Tamper secure circuitry including a first printed circuit board having mounted thereon circuit components and a slotted anti-tamper grid containing printed circuit board mounted onto the first printed circuit board defining at least one slot and arranged to overlie at least some of the circuit components, which are located in a volume defined by the at least one slot and the first printed circuit board.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 26, 2013
    Assignee: Verifone, Inc.
    Inventor: Ehud Kirmayer
  • Patent number: 8592689
    Abstract: On a multilayer wiring board which has a plurality of wiring pattern stacked in sequence separately from one another, insulating members each positioned between the plurality of wiring patterns, and interlayer connection bodies electrically connecting the plurality of wiring patterns and in which a voltage conversion IC is built in, a first capacitor, a second capacitor, and an inductor are mounted, the other of electrode portions in the first capacitor or one of electrode portions in the second capacitor is positioned between an input section of the first capacitor and the inductor, and the other of the electrode portions or the one of the electrode portions is electrically set to ground.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 26, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Osamu Shimada
  • Patent number: 8592688
    Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 26, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Patent number: 8581104
    Abstract: A wiring board includes an insulation layer containing a resin and a silica-type filler and having a roughened surface, and a conductive layer formed on the roughened surface of the insulation layer and having a first conductive portion and a second conductive portion positioned adjacent to the first conductive portion. The roughened surface of the insulation layer has a roughness under the first conductive portion, a roughness under the second conductive portion, and a roughness between the first conductive portion and the second conductive portion, and the roughness between the first conductive portion and the second conductive portion is set less than at least one of the roughness under the first conductive portion and the roughness under the second conductive portion.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: November 12, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Toru Nakai, Tetsuo Amano, Yoshinori Takasaki
  • Patent number: 8581105
    Abstract: A process of making an article of manufacture, the process including constructing an electrical device which implements circuitry having a portion in cavities, the portion defined by an epoxy dielectric material delivered with solid content sufficient that etching the epoxy forms cavities located in, and underneath an initial surface of, the dielectric material, sufficient that the etching of the epoxy uses non-homogeneity with the solid content in bringing about formation of the cavities and sufficient that the etching of the epoxy is such that a plurality of the cavities have a cross-sectional width that is greater than a maximum depth with respect to the initial surface, wherein the etching forms the cavities, and a conductive material, a portion of the conductive material in the cavities thereby forming teeth in the cavities, such that the conductive material forms the portion of the circuitry of the electrical device.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 12, 2013
    Inventors: Brian J. McDermott, Daniel McGowan, Ralph Leo Spotts, Jr., Sid Tryzbiak
  • Patent number: 8581109
    Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and at least some conductor material of the conductor layer is removed from outside the conductor pattern.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: November 12, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola, Petteri Palm
  • Patent number: 8581117
    Abstract: A plurality of conductive areas is formed on a conductive substrate which includes a frame. Each of the conductive areas includes a lead frame and two electrodes. The frame includes a first side and an opposite second side. The lead frame includes first and second lead frame beams. The first and second lead frame beams extend from the first side toward the second side to connect with the two electrodes. The first and second electrodes extend respectively from the first and second lead frame beams. Each conductive area also includes a supporting portion interconnecting the electrodes and the frame to reinforce the connection between the frame and the conductive area so that the conductive area can sustain a pressure when an insulation shell is injection molded on the conductive area.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: November 12, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Pi-Chiang Hu, Kai-Lun Wang
  • Patent number: 8575491
    Abstract: A shielded electrical cable is disclosed that includes a plurality of spaced apart conductor sets where each conductor set includes one or more insulated conductors. The cable further includes first and second shielding films that include concentric portions, pinched portions, and transition portions arranged such that the concentric portions are substantially concentric with one or more end conductors of each conductor set, the pinched portions form pinched portions of the cable on two sides of the conductor set, and the transition portions provide gradual transitions between the concentric portions and the pinched portions. The cross-sectional areas of the transition portions are less than the cross-sectional areas of the conductors. The radius of curvature of the shielding films in the transverse direction is at least 100 microns.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: November 5, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Douglas B. Gundel, William V. Ballard, Alexander W. Barr, Joseph N. Castiglione, William J. Lee, Mark M. Lettang, Jesse A. Mann, Richard J. Scherer, Charles F. Staley
  • Patent number: RE44586
    Abstract: The embodiment of the invention is about a novel via structure which can be incorporated into printed circuit boards, integrated circuit packages, and integrated circuits in order to reduce crosstalk, to improve signal integrity and to achieve EM emission compliance. A 4-layer (2 signal layers and 2 power layers or 2 signal layers and 2 ground layers) circuit board assembly was used for demonstrating the effect of the novel via structure. The same concept can be applied to any multi-layer circuit board. Layers that have an electrical property can be added above, under, or within the basic 4-layer circuit board to achieve a multi-layer circuit board. For 2-layer and 3-layer circuit boards, a deformed version of the proposed via structure based upon the same concept will be needed for a coplanar waveguide configuration.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 12, 2013
    Inventors: Hsiuan-ju Hsu, Richard Walter Ziolkowski