Patents Examined by Jesse A Fenty
  • Patent number: 7372128
    Abstract: The invention discloses an integrated circuit anti-interference outline structure for applications of integrated circuits capable of shielding the integrated circuit from invasions of external electromagnetic waves and leaks of internal electromagnetic waves, wherein the integrated circuit anti-interference outline structure surrounds a periphery of a partial circuit within the integrated circuit and comprises a plurality of PNP structures. At a surface of the integrated circuits are two metal strips for producing a parasitic capacitance at poly layers in order to control noises within acceptable ranges. On a P-substrate therein is disposed with a deep N-well layer for connecting to an N-terminal of an N-well layer, so as to produce a positive voltage zone having a large area, and thus having noise currents overflow from a ground terminal as well as preventing the integrated circuit from invasions and leaks of electromagnetic waves.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: May 13, 2008
    Assignee: Alcor Micro, Corp.
    Inventors: Jean-Jen Cheng, Pei-Sung Chuang
  • Patent number: 7323781
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: January 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwaskai, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 7291927
    Abstract: A dual chips stacked packaging structure. A first chip comprises an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads. A lead frame comprises a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, with the first adhering surface adhering to the active surface of the first chip in such a way as to avoid contact with the first bonding pads. A second chip comprises an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, and the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads. Parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: November 6, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Chen-Jung Tsai, Chih-Wen Lin
  • Patent number: 7279743
    Abstract: Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: October 9, 2007
    Assignee: Vishay-Siliconix
    Inventors: Deva N. Pattanayak, Robert Xu
  • Patent number: 7268387
    Abstract: The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very narrow. A channel region of a memory transistor is divided into two regions of a writing control region and a writing region. The writing control region and the writing region have different threshold voltages. Writing is only carried out in the writing region. The writing control region turns off when the amount of electric charges accumulated in a floating gate reaches a specific value due to writing. The writing control region is used as a switch for a writing operation to automatically stop writing. Accordingly, an involatile memory comprising a memory transistor, in which writing can be carried out at a high speed with low consumption power and which is superior in controlling a threshold voltage after writing or erasing, can be obtained.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Kiyoshi Kato
  • Patent number: 7256436
    Abstract: In a thin-film field-effect transistor having a MIS structure, the insulator layer is formed of cyanoethylated dihydroxypropyl pullulan. The TFT is prepared by applying a cyanoethylated dihydroxypropyl pullulan solution onto a gate electrode in the form of a metal layer, drying the applied solution to form an insulator layer, and thereafter, forming a semiconductor layer thereon.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 14, 2007
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Ikuo Fukui
  • Patent number: 7247876
    Abstract: A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventor: Tyler A. Lowrey
  • Patent number: 7244979
    Abstract: A semiconductor memory device includes a substrate having a semiconductor element formed thereon, an interlayer dielectric layer formed above the substrate, a plug formed in the interlayer dielectric layer, an adhesion layer formed in a region including a region above the plug, and a ferroelectric capacitor formed above the adhesion layer and having a lower electrode, a ferroelectric layer and an upper electrode, wherein an oxidized layer is formed in a part of the adhesion layer at a side wall thereof.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: July 17, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Yukihiro Iwasaki, Tatsuo Sawasaki, Kazumasa Hasegawa
  • Patent number: 7242094
    Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: July 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Matsunaga, Yuichi Nakashima, Koji Miyamoto
  • Patent number: 7235831
    Abstract: In order to reduce the capacitance of a light-receiving element, the present invention provides a light-receiving element which includes a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, provided on the first semiconductor region, a third semiconductor region of the first conductivity type, provided between the second semiconductor region and an insulating film and an electrode region of the second conductivity type, provided in the second semiconductor region where the third semiconductor region is absent on and above the second semiconductor region, and connected to an anode or cathode electrode consisting of a conductor.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: June 26, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiraku Kozuka, Toru Koizumi, Koji Sawada
  • Patent number: 7233018
    Abstract: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: June 19, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Kyun Cho, Sung Ku Kwon, Tae Moon Roh, Dae Woo Lee, Jong Dae Kim
  • Patent number: 7233027
    Abstract: The invention relates to an arrangement comprising at least two different electronic semiconductor circuits (HS) in which each of the semiconductor circuits (HS) is a component made of semiconductor material and which has an electrically active surface and electronic contacts, and corresponding contacts of the semiconductor circuits are connected to one another in an electrically conductive manner. In order to simplify production, the semiconductor circuits (HS) are produced in a common support (12) made of semiconductor material and are connected to one another in an electrically conductive manner. Electrically conductive contacts (18) that are connected to the semiconductor circuits (HS) are produced on the surface of the support (12) by metallizing the support. Said support (12) has an expansion (13), which is made of the same material, forming a unit with the same, and which is provided for accommodating additional switching elements or components.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: June 19, 2007
    Assignee: Merge Optics GmbH
    Inventors: Dag Neumeuer, Martin Brahms
  • Patent number: 7230315
    Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 12, 2007
    Assignee: STMicroelectronics S.r.L.
    Inventors: Gabriele Barlocchi, Ubaldo Mastromatteo, Flavio Francesco Villa
  • Patent number: 7227193
    Abstract: A solid-state image sensor prevents shading while maintaining the wide dynamic range of an image signal without reducing its resolution. The image sensor has its photodiode array including arrangement patterns, each of which includes a smaller micro-lens and larger micro-lenses arranged on the top, bottom, right and left sides of the smaller micro-lens in a first virtual plane formed by the array. When the arrangement pattern is viewed in parallel to the virtual plane through a gap between the larger micro-lenses positioned on the bottom and left sides of the smaller micro-lens in the plane, the image of an unhidden part of the smaller micro-lens visible through the gap is, at most, half as much in area as the whole image of the smaller micro-lens projected on a second virtual plane perpendicular to the first virtual plane.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: June 5, 2007
    Assignee: Fujifilm Corporation
    Inventor: Kazuya Oda
  • Patent number: 7227172
    Abstract: In a Group-III-element nitride semiconductor device including a Group-III-element nitride crystal layer stacked on a Group-III-element nitride crystal substrate, the substrate is produced by allowing nitrogen of nitrogen-containing gas and a Group III element to react with each other to crystallize in a melt (a flux) containing at least one of alkali metal and alkaline-earth metal, and a thin film layer is formed on the substrate and the thin film has a lower diffusion coefficient than that of the substrate with respect to impurities contained in the substrate. The present invention provides a semiconductor device in which alkali metal is prevented from diffusing.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: June 5, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Kazuyoshi Tsukamoto
  • Patent number: 7227263
    Abstract: A semiconductor device includes a semiconductor chip which has a top surface, a conductive member which includes a first portion which is located on the electrode pad and a second portion which is extended from the first portion, and a sealing resin which seals the top surface of the semiconductor chip and the conductive member. A top surface of the second portion is exposed from the sealing resin and a part of the top surface of the second portion is concaved from a surface of the sealing resin. An external electrode is formed on the top surface of the second portion.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 5, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tadashi Yamaguchi
  • Patent number: 7220985
    Abstract: An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: May 22, 2007
    Assignee: Spansion, LLC
    Inventors: Patrick K. Cheung, Ashok M. Khathuria
  • Patent number: 7208759
    Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomomi Momohara
  • Patent number: 7190012
    Abstract: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating layer and an intermetal insulating layer and an interconnecting structure, exposing the etching blocking layer by etching the intermetal insulating layer and the interlayer insulating layer, removing a portion of the etching blocking layer and the buffer oxide layer of the light-receiving unit by dry etching, and exposing a semiconductor surface of the light-receiving unit by wet etching.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Sung Son, Sung-Ryoul Bae, Dong-Kyun Nam
  • Patent number: 7187036
    Abstract: A semiconductor contact connection structure and the method for forming the same are disclosed. The connection structure has a first semiconductor device formed on an insulator substrate. A non-conducting gate interconnect layer is formed on the insulator substrate for connecting to a gate of a second semiconductor device, and a silicide layer formed on the gate interconnect layer and an active region of the first semiconductor device for making a connection thereof.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: March 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jhon Jhy Liaw