Abstract: The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device including an array having memory cells having columnar structures and a floating gate structure interposed between the structures that is positioned closer to one of the structures. In another embodiment, a memory device includes an array having memory cells having adjacent FETs having source/drain regions and a common floating gate structure that is spaced apart from the source/drain region of one FET by a first distance, and spaced apart from the source/drain region of the opposing FET by a second distance. In still another embodiment, a memory device is formed by positioning columnar structures on a substrate, and interposing a floating gate between the structures that is closer to one of the structures.

Abstract: A gallium-nitride based light-emitting diode structure includes a digital penetration layer to raise its reverse withstanding voltage and electrostatic discharge. The digital penetration layer is formed by alternate stacking layers of AlxInyGa1-x-yNzP1-z/AlpInqGa1-p-qNrP1-r, wherein 0?x,y,z,p,q,r?1, and AlxInyGa1-x-yNzP1-z has an energy gap greater than that of AlpInqGa1-p-qNrP1-r. The AlxInyGa1-x-yNzP1-z layers have increasing thickness and the AlpInqGa1-p-qNzP1-r layers have decreasing thickness.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: An optoelectronic assembly for an electronic system includes a transparent substrate having a first surface and an opposite second surface, the transparent substrate being thermally conductive and being metallized on the surface. A support electronic chip set is configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions and is bonded to the second surface of the transparent substrate. A first substrate having a first surface and an opposite second surface, is in communication with the transparent substrate via the metallized second surface and support chip set therebetween. A second substrate is in communication with the second surface of the first substrate and is configured for mounting at least one of data processing, data switching and data storage chips.

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 ? (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract: A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

Abstract: A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2). The second diffusion region (6) is formed in a predetermined upper surface area of the epitaxial region (3). The second diffusion region (6) has a central portion (6a) and a peripheral portion (6b). The central portion (6a) is formed substantially at the center of the epitaxial region (3) and formed thicker than the peripheral portion (6b). The peripheral portion (6b) is formed in an annular shape so as to surround the central portion (6a). The drain region (7) is formed in an upper surface area of the central portion (6a) of the second diffusion region (6).

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A lateral high-voltage junction device for over-voltage protection of an MOS circuit includes a substrate having a first junction region separated from a second junction region by a substrate region. An MOS gate electrode overlies the substrate region and is separated therefrom by a gate dielectric layer. Sidewall spacers reside adjacent to opposing sides of the MOS gate electrode and overlie the substrate region. The substrate region is defined by a junction-free semiconductor region between the first and second junction regions. An input protection circuit employs the lateral high-voltage junction device to transfer voltage transients to a ground node.

Abstract: M pieces of n-well regions nW are provided on a main surface of a p-type silicon substrate 3, and p-well regions pW are provided among the n-well regions adjacent to one another. Moreover, each of the M pieces of n-well regions nW includes an n-type diffusion region nD and a p-type diffusion region pD1, which are formed therein. Furthermore, the p-well region pW includes a p-type diffusion region pD2 therein. The n-type diffusion region nD in a j-th of the n-well region nW is connected to the p-type diffusion region pD1 in a (j+1)-th of the n-well region 10. The p-type diffusion region pD1 in the first n-well region nW is connected to a first terminal 1. The n-type diffusion region nD in the M-th of the n-well region nW is connected to a second terminal 2.

Abstract: A silicon based semiconductor device and method uses charge trapping to alter a density of carriers available in a channel of a field effect transistor (FET) for conduction. The charge trapping mechanism can be controlled by a source-drain bias voltages applied to the FET, so that the device can be turned off through a control mechanism separate from a gate voltage.

Abstract: The semiconductor device includes a multilevel interconnection formed on a semiconductor substrate. The multilevel interconnection includes a plurality of wiring layers each of which is insulated by an insulating layer. A metal member is formed as a shielding film in a same plane as a wiring layer. As a result, the shielding layer can be formed without increasing the number of process steps.

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

Abstract: A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.

Abstract: The invention provides a TFT electrode structure and its manufacturing method that can prevent metal diffusion occurring in the fabrication of a TFT, and thereby reduce the risk of contamination of the chemical vapor deposition process due to metallic ion diffusion. The transparent pixel electrode is formed after the gate electrode metal so that the pixel transparent electrode can be used as a barrier layer to prevent metal diffusion under high temperature from the gate electrode metal to adjacent insulating layers or the active layer. Further, the method used to form the transparent pixel electrode is a low-temperature physical vapor deposition process, which affected less by the processing environment, and the transparent pixel electrode is a conductive layer that is not affected by metal diffusion.

Abstract: An insulated gate semiconductor device includes a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer; a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the second base layer a channel electrically connecting between the source layer and the first base layer, wherein the voltage transiently applied to the device is larger than the static breakdown voltage between the source and the drain when a rated current is turned off under a condition, in which condition the device is connected to an inductance load without using a protective circuit.

Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.

Abstract: A conductive material such as silver is charged in a via hole of an insulative substrate made of low-temperature-sintered ceramic. A lower electrode, a dielectric layer, and an upper electrode are formed in a thin film on the insulative substrate. Thus a thin-film capacitor element is formed in which the capacitance value of the capacitor is specified by the overlapping part of the lower electrode and the upper electrode opposed through the dielectric layer. The dielectric layer is shaped like a ring with the via hole (conductive material) as the center and the part exposed inward from the inner periphery of the dielectric layer is served as a lead section of the lower electrode. The lead section is connected to a ground electrode on the back of the insulative substrate through the conductive material.

Abstract: In a terminal, a semiconductor device, a terminal forming method and a flip chip semiconductor device manufacturing method, it is possible to lessen damage to a semiconductor element due to vibration caused by an ultrasonic wave and settle misalignment and height unevenness of terminals. The terminal includes a pad provided on an active surface of an electric element having an IC chip, a metal post connected to the pad, and a projection electrode provided on the metal post.

Abstract: A camera includes a charge-coupled device having a substrate or well of a first conductivity type; a buried channel of a second conductivity type; a dielectric disposed on the substrate; six gates disposed on the dielectric that are space oriented sequentially 1 through 6 in which six gates, in a first mode, receives signals in which alternating gates receive substantially complimentary clock cycles, and in a second mode the gates receive signals in which gates 1 and 4 receive complimentary clock cycles and gates 2 and 5 are approximately held at a first constant voltage and gates 3 and 6 are approximately held at a second constant voltage.