Abstract: A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

Abstract: A method for protecting memory is provided. The method includes reading a block of data from a storage drive and writing the block of data to a first memory portion and a second memory portion. The method also includes managing the first memory portion and the second memory portion to protect the block of data. The block of data can be recovered from a non-failing portion in case either the first memory portion or the second memory portion fails.

Abstract: A SCSI-to-IP cache storage system interconnects a host computing device or a storage unit to a switched packet network. The cache storage system includes a SCSI interface (40) that facilitates system communications with a host computing device or the storage unit, and an Ethernet interface (42) that allows the system to receive data from and send data to the Internet. The cache storage system further comprises a processing unit (44) that includes a processor (46), a memory (48) and a log disk (52) configured as a sequential access device. The log disk (52) caches data along with the memory (48) resident in the processing unit (44), wherein the log disk (52) and the memory (48) are configured as a two-level hierarchical cache.

Abstract: A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.

Abstract: An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments advantageously enhance the throughput of the MRAM and a related digital circuit, such as a computer system, which advantageously enhances the operating speed of the digital circuit.

Abstract: A storage system conducting remote copy functions such that, when data is updated at a local site, contents of the update can be referred to in real time by storage at a remote site. A disk-control unit at a remote site receives file data written in accordance with an update of a file in a storage system at a local site and a history of the file-management information from the storage system at the local site and stores the data and the history. A file-system processing unit refers to the history and updates the file-management information in a file-system cache in accordance with the update of the file in the storage system at the local site. When a client issues a read request, the file-system processing unit refers to the file-management information updated in the file-system cache and transfers the contents of the update of the file to the client.

Abstract: Systems and associated methods provide a level of indirection between multiple host computers and multiple data storage resources, such as removable media data storage devices. At least one of the hosts is not provided with direct access to some of the removable media data storage devices. Instead, logical addresses are provided to the host computers, where the logical addresses can relate to physical addresses associated with the data storage resources. A data storage resource handle or logical proxy may be presented to a host, and a management layer determines whether the host receives access to physical data storage resources, or virtual resources that emulate the physical resources.

Abstract: A content addressable memory (CAM) device for use in various sizes of systems while requiring minimal circuitry to enlarge the size of the prioritization circuitry. In smaller systems, the CAM device determines the highest priority CAM device having a match. In larger systems, an external logic device determines the highest priority CAM device having a match and then provides that information to each CAM device in the system. In both smaller and larger systems the CAM device determines if it is the highest priority CAM device having a match. In accordance with an exemplary embodiment of the invention, the CAM device needs only minimal programming to be configured to be utilized in either a larger or smaller system.

Abstract: A technique for maintaining order among a plurality of entities contained in an intermediate node by ensuring orderly access to a resource shared by the entities. A request is generated to access the resource. The request is placed on a queue associated with an entity. The request eventually reaches the head of the queue. An identifier generated by a gate manager is compared with an identifier associated with the queue to determine if they match. If so, the request is transferred to the resource, which processes the request. Results acquired from the resource (if any) are transferred to the entity.

Abstract: A system for backing up data includes a first computer configured to access a first storage device and a second computer configured to access a second storage device. In particular, the first storage device includes data to be backed up and the second storage device includes a snapshot of the data to be backed up. This system also includes a communications pathway between the first and second computers; and a backup application on the second computer which can backup the snapshot in response to a backup request initiated by the first computer.

Abstract: A system for quickly accessing user permissions in an access control list includes a first cache memory (2), a second cache memory (3), a permission querying module (12), a permission merging module (13), and an information unit generating module (14). The first cache memory is for storing a plurality of first information units (20). The second cache memory is for storing a plurality of second information units (30). The permission querying module is for querying the user permissions stored in the first cache memory and the second cache memory, and respectively storing first information units and second information units in the first cache memory and the second cache memory. The permission merging module is for merging different user permissions. The information unit generating module is for generating the first information units and the second information units. A related method is also disclosed.

Abstract: A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM.

Abstract: The invention provides a storage and retrieval routine for Web objects. A Web page typically includes several objects such as text, images and hyper-links to other Web pages. Each Web page and its objects are usually stored in separate files. A storage and retrieval routine stores objects that correspond to the same Web page in co-located positions on a disk. Therefore, when the Web page and its embedded and hyper-linked Web objects are retrieved, the seek time is reduced, thereby reducing the object retrieval time as perceived by a computer user and increasing the number of requests per second that a Web content server can deliver.

Abstract: A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the active devices that initiate the transactions. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node.

Abstract: A data memory for storing elements, which data memory stores the data of the elements and at least a chained list which contains, for each stored element, at least its element address, its element number and a pointer to the address of the stored element having the next-higher element number. There are also provided an element status table, in which the element numbers of the elements present in the data memory are taken up, and also an address reference table which contains the element addresses for all element numbers.

Abstract: A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Abstract: A method and apparatus for mirroring data stored in a storage device in a mass storage system by caching mirror coherency synchronization operation requests (break mirror and/or snapshot) from the operating system of a server and rapidly sending an acknowledgement to the server that the mirror operation has been completed. Thereafter, the mass storage system performs the flushing and mirroring processes to establish a mirror of the storage device at a time that is appropriate and convenient for the mass storage system to perform such mirroring. To facilitate such a mirror operation at a later time, the mass storage system may utilize a mirror table containing information concerning the mirror request. This information enables the mass storage system to subsequently flush the cache of data that is pertinent to a time before the mirror request occurred. Consequently, the mirror operation only mirrors data that would have been available for mirroring at the time the mirror request was received from the server.

Abstract: A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status vector, and generates a match vector as a function of the status vector and a set of stored compare vectors. In response, the OA selects for output one of a set of a control vector as a function of the match vector. A state vector portion of the selected control vector is forwarded to the CAM as a portion of the status vector. An output vector portion of the selected control vector controls the operation of external components. Both the set of stored compare vectors and the set of control vectors are fully re-programmable.

Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory. For example, it may be arranged for a read request to be transmitted to a ternary content addressable memory unit. Data content may then be received from the memory unit in response to the read request, a parity check may be performed on the data content. According to some embodiments, parity information may be masked when the memory unit is queried.

Abstract: Methods, apparatus and machine readable medium are described in which BIOS initialization code divides one or more storage devices into two or more portions. Further, a BIOS device handler may use the portions of the divided storage devices to implement a storage array that provides attributes of one or more RAID levels.