Abstract: A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency. A node is formed by a group of clients which share a common address and data network. The address network determines whether a transaction is conveyed in broadcast mode or point-to-point mode. The address network includes a table with entries which indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may access the table to determine the transmission mode which corresponds to the received transaction. Network congestion may be monitored and transmission modes adjusted accordingly. When network utilization is high, the number of transactions which are broadcast may be reduced.

Abstract: Setting a plurality of table entries in a storage device includes subdividing the table entries into a N tasks, placing each of the N tasks in a memory location disposed within the storage device and accessible by a plurality of internal devices, the plurality of the internal devices accessing the memory location to retrieve at least one of the N tasks, and each of the plurality of the internal devices setting table entries corresponding to at least one of the N tasks retrieved from the memory location. Setting table entries may also include setting logical device table entries to indicate corresponding tracks contain invalid data in connection with operation of remote data transfer between multiple storage devices.

Abstract: A software architecture for automatically (i.e., programmatically) determining a storage configuration of a storage system for a certain software application. Software programs which determine the storage configuration may have a modular software architecture that allows the software programs to be used for a plurality of different types of software applications. A storage configurator core engine program may be executable to perform the automatic storage configuration function that is independent of, or generic to, a plurality of possible software applications. The core engine program may be configured to interface with one of a plurality of possible application specific programs, depending on the software application for which the storage configuration is being determined. The core engine program may also be configured to interface with other programs or files in performing the automatic storage configuration function, such as a rule information file, a free space file, and user input.

Abstract: The invention provides a method and system for staging write data to improve a storage system's performance. The method includes providing a write cache on the medium. The write cache includes a plurality of cache lines. Each of the cache lines includes a plurality of data blocks, line meta-data to identify each data blocks sector address, and a sequential number indicating the order of the data blocks within their respective cache line relative to the other data blocks in the cache line. In addition, the method includes staging write data in the write cache as sequentially written data to improve performance of the system. The staging includes receiving a plurality of data blocks to be written to the system. Moreover, the staging includes storing the data blocks in one of the cache lines.

Abstract: A method for using a memory area of a mobile communication terminal is disclosed. The method is directed toward managing a personal information manager (PIM) in a mobile telecommunication phone. A memory area is assigned to each field and an index number is designated according to a type of data in the memory area. For inputting data in a memory area, the user inputs data in a memory, searches for existence of a corresponding index of the entered data, and updates the relevant data based on the search result. The useable area of memory is thus expanded and more efficiently used by classifying available memory areas and designating an index number to each field.

Abstract: A content addressable memory (CAM) device (100) may include a number of sub-blocks (102-8 to 102-15) that can generate CAM search results. In a “search beyond” operation, sub-blocks (102-8 to 102-15) may be excluded from a search operation according to criteria, including a sub-block address and a soft-priority value. A CAM device may include a compare circuit (400) that may compare sub-block address values in a time division multiplexed fashion to establish priority from among multiple CAM sub-blocks.

Abstract: A memory provides a programmable write port data width and an independently programmable read port data width. The independence between the programmable write port data width and the programmable read port data width is achieved without the use of a third clock domain.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: When a request to conduct format process is received from the external device, a write history management table which records histories of conducted writing processes in block units is referred to confirm whether or not writing process has been conducted to the block. As a result of the confirmation, the format process is conducted to only a block, which a writing process has not been conducted, and a history of conducting the writing process of the formatted block is recorded. In conducting the format process, when a request is received to conduct reading process and/or writing process from the external device, the write history management table is referred, and only in a case that a writing process has been conducted to said block, the disk array device is accessed and a reading process and/or writing process is conducted to the block.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment associate a persistent indicator with allocated memory and determine whether to preserve the contents of the allocated memory during an IPL (Initial Program Load) based on the persistent indicator. If the persistent indicator associated with the memory is on, the contents of that memory are preserved, and if the persistent indicator is off, the contents of that memory are discarded.

Abstract: Asynchronous memory devices utilize loopback circuitry to provide efficient and high speed “flow-through” of write data when conventional flow-through operations are not available. An exemplary memory device includes a memory array having first and second ports that can each support asynchronous read and write access and a first input/output control circuit. The first input/output control circuit is electrically coupled to the first port and includes a first sense amplifier, which is configured to receive read data from the first port, and a first bypass latch having an output coupled to the first sense amplifier. A second input/output control circuit is also provided. The second input/output control circuit is electrically coupled to the second port and includes a second sense amplifier, which is configured to receive read data from the second port, and a second bypass latch.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding collisions between cache lines containing objects and cache lines containing corresponding object table entries. During operation, the system receives an object identifier for an object, wherein the object identifier is used to address the object in an object-addressed memory hierarchy. The system then applies a mapping function to the object identifier to compute an address for a corresponding object table entry associated with the object, wherein the mapping function ensures that a cache line containing the object table entry does not collide with a cache line containing the object.

Abstract: The present invention is directed to a system and method for increased data availability. In an aspect of the present invention, a method includes receiving a SMART indication from a data storage device included in a plurality of data storage devices configured as a RAID array. Data from the data storage device which originated the SMART indication is replicated to a second data storage device. The second data storage device was not originally configured in the RAID array with the plurality of data storage devices for data storage. The data storage device which originated the SMART indication from the RAID array is removed, thereby resulting the second data storage device and the plurality of data storage devices configured as a RAID array.