Abstract: An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the leakage curent by tailoring the composition of SiCOH.

Abstract: A semiconductor device to be mounted on an external electronic device includes a film substrate on which wiring electrodes are formed, the wiring electrodes being partially covered with a covering member; and a semiconductor chip mounted on the film substrate. In this semiconductor device, the film substrate is folded so that at least one edge of the film substrate is on a side opposite to a side on which the semiconductor chip is mounted, and portions of the wiring electrodes exposed from the covering member on a surface of the film substrate on which the semiconductor chip is mounted are to be connected to electrodes of an external electronic device.

Abstract: Techniques of shallow trench isolation and devices produced therefrom are shown. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device. The shallow trench isolation structures are used on a variety of substrates including silicon-on-insulator (SOI) substrates and silicon-on-nothing (SON) substrates.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of metal oxide having multiple different metals bonded with oxygen. The layer has varying stoichiometry across its thickness. The layer includes an inner region, a middle region, and an outer region. The middle region has a different stoichiometry than both the inner and outer regions.

Abstract: A phosphorus-doped amorphous silicon film and a silicon nitride film are serially grown over a semiconductor substrate. The obtained stack is patterned so as to obtain word lines. A CVD oxide film is grown on the entire surface and then anisotropically etched to thereby form sidewalls on the lateral faces of the word lines. An ONO film previously formed just under the CVD oxide film is also removed by the etching. The semiconductor substrate is etched to thereby form a groove, where masking is effected by the silicon nitride film, silicon oxide film and sidewall. Boron ions are doped by ion implantation through the same mask into the bottom of the groove to thereby form a channel stop impurity-diffused layer. Then, an inter-layer insulating film is formed over the entire surface.

Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Abstract: A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on the insulating layer, a first dielectric layer formed on the first fin, and a partially silicided gate formed over a portion of the first fin and the first dielectric layer. A second device also may be formed on the insulating layer. The second device may include a second fin formed on the insulating layer, a second dielectric layer formed on the second fin, and a fully silicided gate formed over a portion of the second fin and the second dielectric layer.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and comprising a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, at least one of the bottom electrode and the top electrode comprising a conductive film selected from a noble metal film and a noble metal oxide film, a metal oxide film having a perovskite structure, provided between the dielectric film and the conductive film, represented by ABO3, and containing a first metal element as a B site element, and a metal film provided between the conductive film and the metal oxide film, and containing a second metal element which is a B site element of a metal oxide having a perovskite structure, a decrease of Gibbs free energy at a time when the second metal element forms an oxide being larger than that at a time when the first metal element forms an oxide.

Abstract: A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.

Abstract: A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

Abstract: A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: A trench structure of a semiconductor device includes first and second regions of a substrate having first and second trenches, respectively, the first trench having an aspect ratio larger than that of the second trench, a first insulation material on a bottom and sidewalls of the first trench forming a first sub-trench in the first trench, a second insulation material completely filling the first sub-trench, a third insulation material formed on a bottom and sidewalls of the second trench forming a second sub-trench in the second trench, a fourth insulation material formed on a bottom and sidewalls of the second sub-trench, and a fifth insulation material completely filling a third sub-trench formed in the second sub-trench by the fourth insulation material.

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract: A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over the gate insulator, and metallic spacers on sides of the gate conductor.

Abstract: A long life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrode 8 and a degradation preventive layer at the boundary of ferroelectric layer 7/electrodes 6, 8, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer 7/upper electrode 8. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.

Abstract: A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

Abstract: A unit pixel in a CMOS image sensor is employed to reduce a threshold voltage of a reset transistor by modifying a unit pixel circuit. The unit pixel in the CMOS image sensor including: a semiconductor substrate including an epitaxial layer in which an active area and a FOX area are defined; a photodiode formed in the epitaxial layer; a transfer transistor including source/drain regions disposed between the photodiode and a floating diffusion node, wherein a control signal is applied to a gate thereof; a reset transistor including source/drain regions disposed between the floating diffusion node and a VDD terminal, wherein a control signal is applied to a drain thereof; a drive transistor of which a gate is connected to the floating diffusion node and a drain is connected to the VDD terminal; and a selection transistor of which a drain is connected to the drain of the drive transistor and a source is connected to an output terminal, wherein a control signal is applied to a gate thereof.