Abstract: A transistor is protected when a high voltage is applied to a drain, without an increase in the capacitance of the drain. A semiconductor device has a gate electrode on a silicon semiconductor substrate on a gate oxide film, and a pair of N+-type diffusion regions at a surface of a silicon semiconductor substrate on either side of the gate electrode. An N-type diffusion region in the N+-type diffusion region of the drain protrudes to a position deeper in the substrate than the N+-type diffusion region.

Abstract: A method of making and a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer and defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer including a first, a second and a third layers. The first layer formed on the floating gate. The second layer formed on the first layer. The third layer formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (Å) of SiO2.

Abstract: A non-volatile storage cell manufactured in a standard CMOS process in silicon on insulator is described. The cell is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator starting substrates. Two versions of the cell are described with distinct mechanisms for writing onto a floating polysilicon layer storage node. The basic cell comprises crossed N- and P- transistors which share a common channel region and a common floating gate over the channel. Current in the channel results in charge injection through the gate oxide and onto the polysilicon gate conductor where it is permanently stored. Since both N and P type transistors are available, charge of both polarities can be injected. Application of a voltage to either of the transistors results in a current or voltage which is used to perform the reading function. Multiple variations of the cell and its operation are also described along with unique applications of the cell.

Abstract: A non-ceramic image sensor semiconductor package with improved moisture resistance, lower cost, and higher reliability is provided. A semiconductor chip with a vision chip active area is attached to a multi-layer resin mask organic substrate. A plurality of bonding wires are attached between parts of the semiconductor chip and the multi-layer resin mask organic substrate to create selective electrical connections. A castellation is formed to create a riser surrounding the semiconductor chip. The height of the castellations can be made to a desired height so that proper clearance of the semiconductor chip and the glass window is achieved. A transparent window is placed on the top of the castellations. A liquid encapsulant is formed to protectively seal the non-ceramic image sensor semiconductor package thereby shielding the semiconductor chip and vision chip active area from the external environment.

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: The specification describes integrated circuit air isolated crossover interconnections designed for flip chip multi-chip module interconnection technology. The crossovers are made using a crossover interconnection substrate separate from the interconnection substrate of the integrated circuit. In one embodiment the integrated circuit is flip chip bonded to a multi-chip or multi-component interconnection substrate, and the crossover interconnections are made through solder bumps or balls soldered to a conductive layer on the crossover interconnection substrate. In another embodiment the crossover is made via a crossover substrate flip chip bonded to an integrated circuit mounted on a multi-chip or multi-component interconnection substrate.

Abstract: In an IGBT, an n buffer layer is formed under an n− high resistance layer in which a MOS gate structure is formed. An n+ buffer layer is formed between the n buffer layer and a p+ drain layer. Since the p+ drain layer is doped at a low dose, the efficiency of carrier injection can be reduced and a high-speed operation is possible without lifetime control. Since no lifetime control is performed, the on-state voltage can be low. Since the n buffer layer does not immediately stop the extension of the depletion layer during a turn-off period, oscillation of the current and voltage is prevented. The n+ buffer layer maintains a sufficient withstand voltage when a reverse bias is applied.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on the base layer in the shape of a ring along the outer circumference of the base layer, the semiconductor layer includes a ring-shaped emitter region functioning as an emitter, and the outer edge of the emitter region and the outer edge of the base layer are disposed in substantially the same plane position.

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Abstract: A bipolar p-i-n diode has a first (1) and second (5) region of opposite conductivity type and an intermediate drift region (3) between the first and second regions. Trenched field relief regions (14) are arranged to deplete the intermediate drift region (3) when the diode is reverse biased, so permitting a higher doping (12) to be used for the intermediate drift region (3) for a given breakdown voltage. This improves both the turn-on and turn-off characteristics of the diode.

Abstract: Formed on the surface of an n-type semiconductor layer (21) taken as a collector region is a base region (22) consisting of a p-type region, and formed in the p-type region is an emitter region (23) consisting of an n+-type region. Further, provided in the base region is a base electrode connecting portion (24) consisting of an n+-type region, and a base electrode (26) is connected to the surface of the base electrode connecting portion, and an emitter electrode (27) and a collector electrode (28) are provided and connected electrically to the emitter region and the collector region (21), respectively. As a result, a semiconductor device is obtained which has the transistor in which the reduction in power consumption with a high withstand voltage can be achieved, and the fast switching speed is possible and the large current is obtained. Further a voltage-drive type bipolar transistor such as a digital transistor is obtained which is small in load capacity while establishing a desired drive voltage.

Abstract: A semiconductor device of the present invention includes a systematic structure layer of first conductivity type and having a systematically arranged structure. The systematic structure layer is formed on a collector contact layer of first conductivity type, which is connected to collector electrodes. A compensation layer of first conductivity type is formed on the systematic structure layer. A collector layer of first conductivity type is formed on the compensation layer. A base layer is formed on the collector layer and connected to base electrodes. An emitter layer is formed on the base electrode and connected to an emitter electrode. The semiconductor device reduces collector resistance and thereby improves reliability.

Abstract: A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides devices requiring deep ion implant capabilities and/or a high degree of thermal management. A semiconductor device including silicon on insulator regions, strained silicon layer, shallow trench isolation structures, and bulk silicon regions is provided on a single semiconductor substrate.

Abstract: In a semiconductor substrate, semiconductor regions belonging to the IGBT are formed in an IGBT region and semiconductor regions belonging to the diode are formed in a diode region. The IGBT and the diode are connected in anti-parallel to each other. A trench in which an insulator is buried is formed between the IGBT region and the diode region. The insulator restricts the reverse recovery current which flows from the diode region into the IGBT region. Thus, semiconductor regions of an IGBT and a diode connected in anti-parallel with each other are fabricated in a single semiconductor substrate and the chip size is reduced.

Abstract: A UV light sensing element has at least a first electrode and a sensor. The first electrode has a semiconductor containing at least one element selected from Al, Ga and In together with nitrogen or oxygen, and the sensor layer has a semiconductor containing at least one element selected from Al, Ga and In together with nitrogen. A longer wavelength end of an absorption spectrum for the first electrode is located at a position nearer to a shorter wavelength side than a longer wavelength end of an absorption spectrum for the sensor.

Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.

Abstract: A method and structure for a silicon on insulator (SOI) device with a body contact are provided. The body contact is formed by epitaxial growth from a substrate to the body region of the device. The body contact is self-aligned with the gate of the device and is buried within an isolation region outside of the active area of the device. Thus, the body contact does not increase parasitic capacitance in the device, not does the body contact affect device density. No additional metal wiring or contact holes are required.