Abstract: Various embodiments of a wirelessly powered local computing environment are described. The wireless powered local computing environment includes at least a near field magnetic resonance (NFMR) power supply arranged to wirelessly provide power to any of a number of suitably configured devices. In the described embodiments, the devices arranged to receive power wirelessly from the NFMR power supply must be located in a region known as the near field that extends no further than a distance D of a few times a characteristic size of the NFMR power supply transmission device. Typically, the distance D can be on the order of 1 meter or so.

Abstract: A convertible device and a method of controlling therefor are disclosed in the present specification. In this case, according to one embodiment, a convertible device includes at least one of the first processing module and the second processing module that comprises a memory configured to store mode information for a plurality of operational modes of the convertible device, and to store first angle data, a receiving unit configured to receive an input for changing an angle different from an angle of the stored first angle data, a detection unit configured to detect second angle data according to the received input, a controller configured to identify an operational mode of the convertible device based on the first and second angle data and the stored mode information, and control to output a predetermined user interface on the identified operational mode of the convertible device, and an output unit configured to output a predetermined user interface.

Abstract: An integrated circuit includes circuit blocks, a clock network coupled to the circuit blocks, and a supply voltage network coupled to the circuit blocks. Each of the circuit blocks comprises at least one clocked circuit that receives a clock signal. The clock network provides the clock signal to the clocked circuits in the circuit blocks. The supply voltage network provides a supply voltage to the circuit blocks. A latency of the clock signal provided through the clock network to at least one of the circuit blocks is adjusted to decrease a peak voltage drop in the supply voltage caused by a peak current drawn by the circuit blocks.

Abstract: An information processing apparatus is capable of quick launch, in which information of memory is held and the apparatus is launched using the information, and includes an RTC that keeps the time and generates an interrupt at a set time. The apparatus detects whether or not there is an instruction to turn a power supply on or off, and if an instruction to turn the power off is detected, determines whether or not the quick launch is active. If it is determined that the quick launch is active, the apparatus sets an interrupt generated by the RTC inactive.

Abstract: A process calibrator is formed with functions of a fieldbus communicator. Preferably, functions of a fieldbus communicator support several fieldbus protocols, and it is provided such that the use of it does not hamper the functioning of a process calibrator. This has been achieved by providing the process calibrator with a pair of fieldbus connecting terminals for measuring of the fieldbus signal. The process calibrator comprises a processor, and the pair of fieldbus connecting terminals comprises a signal terminal and a ground terminal. The process calibrator further comprises at least two parallel fieldbus protocol units between the processor and the signal terminal of the pair of fieldbus connecting terminals. Each fieldbus protocol unit is dedicated to its respective fieldbus protocol.

Abstract: Embodiments are disclosed for a method of executing instructions in a processing core of a microprocessor. In one embodiment, the method comprises, in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain. The method further comprises synchronizing the input from the second clock domain with the first clock domain, if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction, and otherwise performing the instruction.

Abstract: A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device manages a thermal profile of the device by adjusting a throttling a central processing unit execution of a historically high energy consuming task. In this embodiment, the device monitors thermal level of the thermal profile of the device, the device is executing a plurality of tasks that utilize a plurality of processing cores of the device. If the thermal level of the device exceeds a thermal threshold, the device identifies one of the plurality of tasks as a historically high energy consuming task, and throttles this historically high energy consuming task by setting a force idle execution time for the historically high energy consuming task. The device further executes the plurality of tasks.

Abstract: An electronic apparatus and a booting method thereof are provided. Control a sensing unit to sense a barcode before an operation system is executed by the electronic apparatus. Determine whether the barcode meets a preset barcode. Continue a booting operation of the electronic apparatus if the barcode meets the preset barcode.

Abstract: Embodiments of a USB cable extension system is disclosed for delivering power to a device via a USB connection. The system can include converter circuitries to convert a voltage supplied via a USB connector to a different voltage for transmission over a power transmission wire and to convert a voltage received from a power transmission wire to a different voltage to be supplied to a USB connector connectable to a device to be powered.

Abstract: An analytical device including a main circuit, a main power supply switch and a control unit which acquires measurement data from main circuit and exchanges data with another device. Said analytical device further includes a hard switch and a relay switch which assumes either an ON state in which electric power is supplied to the main circuit or an OFF state in which electric power is not supplied to the main circuit, wherein the control unit, upon receiving input of a first input signal for setting the main power supply switch to an OFF state, if the main circuit is causing the device main body unit to operate, provides notification of the fact that the device main body unit is operating, and upon receiving input of a second input signal for setting the main power supply switch to an OFF state, sets the relay switch to an OFF state.

Abstract: A redundant system is provided with a redundant failure detection configuration, and thereby is enabled to precisely detect a failure occurrence, and reliably execute a necessary system switching operation. In a redundant system 10, each of power supply mechanisms 200 for computers 150, 180 redundantly provided includes a processor 204 configured to: monitor a write process in which predetermined information from another apparatus 300 or another mechanism 112 of the corresponding computer 150 or 180 is written to a storage 201 of the power supply mechanism 200; execute an operation of powering off or resetting a power supply device 230 if the write process is not in conformity with a predetermined rule; and after the execution of the operation, give an instruction to perform a fail-over operation to the other computer out of the computers 150, 180.

Abstract: An implementation of a system disclosed herein provides an apparatus, comprising a system on chip, wherein the system on chip is configured to receive a sleep command from a host and in response to the sleep command, calculate a primary checksum of a block of data from a low latency memory such as a tightly coupled memory (TCM), copy the primary checksum and the block of data into a volatile storage media, preserve interface variables of the system on chip in the volatile storage media, operate the volatile storage media in a self-refresh mode, and shut down power to other components on the system on chip.

Abstract: Apparatus and methods may provide for a central power control unit to grant a power allowance to each of a plurality of computer components and to allocate a shared power pool locally accessible to each of the plurality of computer components when one or more of the plurality of components needs to exceed its granted power allowance.

Abstract: Methods, apparatus, and computer program products are described, which provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices. A receiver device may receive a plurality of symbols over a shared bus, extract a receive clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into data bits, and store at least a portion of the data bits into one or more registers using only the receive clock signal. The receiver device may start a down counter upon detection of a first cycle of the clock signal, trigger a marker when the down counter reaches a pre-defined value, and use the marker to store at least a portion of the data bits into registers.

Abstract: A power control system includes a power supply unit, first and second microcontrollers, a transmission line and first and second filters, for transmitting a power management bus (PMB) to a server. The power supply unit provides a power signal, the PMB and a carrier frequency. The first and second microcontrollers respectively perform modulation and demodulation to the PMB according to the carrier frequency, such that the transmission line simultaneously transmits the power signal and the PMB to the server.

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes a first data transmitting/receiving circuit, a second data transmitting/receiving circuit, and a plurality of channels configured to couple the first and second data transmitting/receiving circuits. The first data transmitting/receiving circuit includes a Tx delay unit configured to transmit data to the plurality of channels, an Rx delay unit configured to receive data from the plurality of channels, and a de-skew control unit configured to control delay amounts of the Tx delay unit and the Rx delay unit according to phase information of reference clock signals received through the plurality of channels.

Abstract: Mechanisms are provided for energy management signalling with an apparatus for processing data, such as a system-on-chip integrated circuit (2). Processing circuitry (6, 8, 10) is coupled to consumer energy interface circuitry (14, 16, 18) which communicates with energy management circuitry (4). The energy management signals which are communicated include a static power consumption signal indicative of a level of power consumption which is independent of processing operations being performed and a dynamic power consumption signal indicative of a level of dynamic power consumption which is dependent upon the processing operations being performed.

Abstract: According to one embodiment, a power control system includes a power controlled unit, a first power controller configured to generate a first control signal that controls the power of the power controlled unit, and a second power controller including a signal holding unit configured to hold the first control signal and to transmit a second control signal including information identical to the information of the first control signal to the power controlled unit, the second power controller being different from the first power controller as hardware.