Abstract: A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory chip in a test socket on a test adaptor board that is connected to the target DRAM module slot to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory chip under test.

Abstract: A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of the motherboard. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory module in the test socket to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory module under test.

Abstract: A method for safely interrupting blocked work in a server including: creating a registry; registering a potential blocking event in the registry; executing the potential blocking event; determining that the potential blocking event is not responding; accessing a registry entry corresponding to the blocking event; and taking an corrective action indicated by the registry entry corresponding to the blocking event.

Abstract: A monitoring system and methods are provided for a distributed and recoverable digital control system. The monitoring system generally comprises two independent monitoring planes within the control system. The first monitoring plane is internal to the computing units in the control system, and the second monitoring plane is external to the computing units. The internal first monitoring plane includes two in-line monitors. The first internal monitor is a self-checking, lock-step-processing monitor with integrated rapid recovery capability. The second internal monitor includes one or more reasonableness monitors, which compare actual effector position with commanded effector position. The external second monitor plane includes two monitors. The first external monitor includes a pre-recovery computing monitor, and the second external monitor includes a post recovery computing monitor. Various methods for implementing the monitoring functions are also disclosed.

Abstract: Provided are a method, system, and article of manufacture wherein a command is received for writing data to a first storage location. A determination is made that previously written data is stored in the first storage location. The previously written data is copied to a second storage location, in response to determining that the previously written data is stored in the first storage location. The data is written to the first storage location, in response to copying the previously written data to the second storage location.

Abstract: A packet switch includes an error management module in addition to various components that facilitate routing of data packets through the packet switch. The components generate error codes indicating errors occurring in the packet switch and provide the error codes to the error management module. The error management module select error codes generated by the components and generates an error log based on the selected error codes. Each component is inhibited from providing the same error code to the error management module more than once until the component receives an acknowledgement for that error code from the error management module. A user can access the error log during operation of the packet switch to monitor performance of the packet switch.

Abstract: A multiple-core, multithreaded processor including a flexible error steering mechanism. An integrated circuit may include processor cores. Each processor core is associated with a respective number of threads and is configured to issue a first instruction from one of the threads during one execution cycle and a second instruction from another one of the threads during a successive execution cycle. An error processing unit may be coupled to the processor cores and configured to detect an error condition corresponding to a data element external to the processor cores. In response to detecting the error condition, the error processing unit may convey an indication of the error to a selected processor core dependent upon an identifier of the selected core. The error indication may also include an identifier of a selected thread executable on the selected processor core. The identifiers of the selected core and the selected thread may be programmable.

Abstract: When data are transferred to a cache from disk drives, through a back end I/F unit, a redundant code verifier of a data path controller compares write-history information (a Destaging Counter (DC) value) embedded in a redundant code of the data with a DC value embedded in a redundant code of a corresponding parity, thereby verifying whether the data are imprecise. In addition, in a case where the data are updated, the redundant code verifier makes a similar verification when old data to be used for creating a parity are read. When the data are not imprecise, a redundant code generator of the data path controller adds to new data and the parity a redundant code into which a new DC value has been embedded. When the data are imprecise, a controller informs a host of an occurrence of a problem through a front end I/F unit.

Abstract: Information handling system errors are presented at a display with the information handling system graphics subsystem inoperative by communicating an identified error to the display through an auxiliary channel and generating a presentation of the error information with a microcontroller of the display. For example, errors determined by BIOS firmware running on a chipset are communicated through a DDC or I2C channel from the chipset to the display so that textual error messages are generated at the display without the use of the information handling system's graphic processor to generate an error message image.

Abstract: A method of providing error notification in a storage subsystem includes writing a first defined value by a host adapter of the storage subsystem to a system management interrupt (SMI) register to generate a hardware interrupt, registering and handling the hardware interrupt by a kernel module of the storage subsystem, writing a second defined value to a shared memory location of the storage subsystem by the kernel module, and reading a shared memory offset value by the host adapter. A system for providing error notification in a storage subsystem includes a controller including a serial management interface (SMI) register subcomponent, a first processing component connected to the controller having a kernel module, and a second processing component connected to the controller executing host adapter software.

Abstract: Use of configuration information to specify particular conditions under which trace events are to be logged. When accessing trace events generated by various modules, configuration data is referred to specifying condition(s) under which the trace events should be logged. If the log condition(s) are satisfied, the trace events are logged. Otherwise, they may be discarded. Thus, the number of trace events in the log may be significantly reduced to those trace events that satisfy conditions of interest to an evaluator.

Abstract: A method for dispatching a remote debugging agent (RDA), involving embedding the RDA in a target program to obtain a remotely debuggable target program, submitting the remotely debuggable target program to a distributed computing environment, wherein the distributed computing environment includes a plurality of nodes, executing the remotely debuggable target program on at least one of the plurality of nodes, establishing a connection between the RDA and a central debugging tool, and debugging the remotely debuggable target program using the central debugging tool.

Abstract: An integrated circuit device has a function block to perform a core function, a bus controller through which the function block is to communicate with another device over an attachment bus, and an error correction module (ECM). The ECM adapts a bus protocol to a failure in the bus, so that the bus protocol remains functional for the function block to communicate with the other IC device via the bus controller, despite the failure. Other embodiments are also described and claimed.

Abstract: A storage protocol test server interfaced with a storage device and a client includes a multi-layered architecture for testing a conformance of the storage device to a storage protocol as dictated by the client. The layers operate to participate in a test case session between the server and the client to facilitate a communication of test case information from the client to the server, the test case information specifying elements for testing the conformance of the storage device to the storage protocol. Additionally, the layers operate to create a storage protocol conformance test based on the test case information received from the client, the test being specifically designed for testing the conformance of the storage device to the storage protocol, and to participate in a test session between the server and the storage device to facilitate an exchange of test instructions and test results in accordance with the test.

Abstract: Embodiments include methods, apparatus, and systems for containing machine check events in a virtual partition. One embodiment is a method of software execution. The method divides a hard partition into first and second virtual partitions and attempts to correct an error in a firmware layer of the first virtual partition. If the error is not correctable, then the method reboots the first virtual partition without disrupting hardware resources in the second virtual partition.

Abstract: Automatic Protection Switching (APS) and error signal processing coordination apparatus and methods are disclosed. If a communication module that enables communication signals and error signals to be exchanged with a remote communication module is configured in an APS protection group, error signal processing by the communication module is restricted. This prevents Time Division Multiplexing (TDM) T1/E1 Remote Defect Indication (RDI) signal processing, for example, from interfering with Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) unidirectional One-plus-One APS. Under certain conditions, however, a restricted communication module may be allowed to perform a restricted error processing operation or revert to normal unrestricted error signal processing.

Abstract: A method for assisting a user to connect a problem with a device, such as a printer includes extracting, from records comprising user actions on the device, string of user actions on the device. The string of user action is compared with at least one predetermined sequence of user actions for correction of predefined problem with the device. Based on the comparison, an evaluation is made as to whether at least one prior user has attempted the predetermined sequence and, if so, a procedure is implemented to avoid a user repeating the prior attempt.

Abstract: The present invention is to provide a method for reconstructing data in case of failure of two HDs of a RAID, wherein the RAID is a logical disk drive assembly including at least three HDs and a RAID controller and data is divided into block strips which are stored on data blocks of different HDs respectively, The method comprises the steps of reading super blocks of all of the HDs; comparing the number of the HDs and time being involved in a previous operation and stored in the super blocks with each other; reading common data involved in the previous degraded operation of the RAID; writing the read common data into the super blocks of all of the HDs; and recovering a configuration of the RAID to the degraded mode again.

Abstract: In an abnormality diagnosis system of the invention where multiple devices and a server S are interconnected via a network, a communication failure may occur between the server S and one device (diagnosis object printer P1) among the multiple devices. On the occurrence of the communication failure, the server S instructs another device (diagnosis execution printer P2) among the multiple devices other than the diagnosis object printer P1 to make a diagnosis of abnormality in the diagnosis object printer P1. In response to the instruction, the diagnosis execution printer P2 obtains communication setting information from the diagnosis object printer P1, and compares the obtained communication setting information with own communication setting information stored in the self printer or the diagnosis execution printer P2.

Abstract: Fault tolerance is provided for a database of hyperlinks distributed across multiple machines, such as a scalable hyperlink store. The fault tolerance enables the distributed database to continue operating, with brief interruptions, even when some of the machines in the cluster have failed. A primary database is provided for normal operation, and a secondary database is provided for operation in the presence of failures.