Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the "loops" formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

Abstract: A method of manufacturing an embossed metal gasket includes the steps of supplying a metal gasket preform having opposed first and second planar surfaces and at least one sealing port defined therein, laminating the opposed planar surfaces with a chemical resist material, masking the chemical resist material on the first planar surface in such a manner so as to delineate a raised surface area of a bead circumscribing the sealing port, masking the chemical resist material on the second planar surface in such a manner so as to delineate a recessed surface area of the bead circumscribing the sealing port, curing the unmasked chemical resist material on the opposed planar surfaces of the preform, removing the uncured chemical resist material from the opposed planar surfaces, and exposing the gasket preform to a chemical etching agent to reduce the thickness of the gasket preform in areas which are absent cured chemical resist material.

Abstract: A method for fabricating a chip carrier, such as a printed circuit board, which includes at least one through hole or via hole, is disclosed. In accordance with this method, an electrically conductive layer is formed on at least one of the major surfaces of the corresponding chip carrier substrate, as well as for the surface of the through hole or via hole. Significantly, the electrically conductive layer on the at least one major surface is relatively thin, which permits the formation of a relatively high density of circuit lines in this layer. On the other hand, the electrically conductive layer on the surface of the through hole or via hole is relatively thick, which prevents the formation of defects in this layer.

Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: A photosensitive composition is provided which prevents deactivation of photosensitive compounds contained therein to provide accurate photoresist pattern shapes. The photosensitive compositions include a photosensitive acid generator, a polyhydroxy-functional resin component and an aliphatic amine. In a preferred embodiment, the photosensitive compositions also may include a bridging agent. The photosensitive compositions preferably contain the aliphatic amine(s) in an amount of from about 0.01% to about 1.0% by weight, based upon the weight of the overall photosensitive composition.

Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development.

Abstract: The present invention provides a heat mode recording material comprising on a flexible support having an oleophilic surface (i) a recording layer containing a light-to-heat converting substance capable of converting radiation into heat and (ii) an oleophobic surface layer, wherein said oleophobic surface layer and said recording layer may be the same layer, characterized in that the kinetic coefficient of friction (.mu..sub.k) of said material when sliding one side of said material over the other side of said material is not more than 2.6.

Abstract: A method for forming a patterned target layer within an integrated circuit. The method employs a plasma pre-treatment of a patterned photoresist layer employed in patterning a blanket focusing which in turn is employed in patterning the patterned target layer from a blanket target layer. The plasma pre-treatment employs a plasma pre-treatment composition comprising carbon tetrafluoride and argon without oxygen. After the plasma pre-treatment, the blanket focusing layer is etched with a reproducible negative etch bias in a plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon without oxygen. Through the method there may be formed patterned target layers, with enhanced uniformity, of linewidth dimension as narrow as about of 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure methods.

Abstract: According to the present invention there is provided a heat sensitive imaging element comprising a lithographic base with a hydrophilic surface, an image forming layer including a hydrophobic thermoplastic polymer latex and a compound capable of converting light into heat being present in said image forming layer or a layer adjacent thereto, characterized in that the image forming layer includes an alkali soluble copolymer containing acetal groups and hydroxy groups which have at least partially reacted with a compound with at least two carboxyl groups.

Abstract: A lead frame etching method, which is used for a semiconductor device assembling process and prevents a sharp-edged portion formed on each lateral end of a lead frame material. The method includes the steps of forming a first photoresist pattern defining the actual etching region, on both surfaces of a lead frame material, forming a second photoresist pattern as an etching buffer extending from lateral ends of the first photoresist pattern, on both surfaces of the lead frame material on which the first photoresist pattern is formed, etching the lead frame material using the second photoresist pattern as an etching mask, removing the second photoresist pattern from the etched lead frame material, etching the lead frame material using the first photoresist pattern as an etching mask, and removing the first photoresist pattern from the twice-etched lead frame material.

Abstract: The semiconductor device disclosed has semiconductor patterns as elements constituting a semiconductor device on a semiconductor substrate. The semiconductor patterns are formed respectively on a first region and a second region on the semiconductor substrate. Between the first region and the second region, there is a stepped portion which is set such that a value S of the step is S=m.lambda./2n wherein .lambda. is a wavelength of the photosensitive illuminating light used in a photolithography process for patterning a photoresist film, m is a positive integer, and n is a refractive index of the photoresist film. The provision of the stepped portion enables the formation of semiconductor element patterns of fine sizes with controllability thereof.

Abstract: A method of forming a conductive plug in an interlevel dielectric includes forming a lower dielectric layer over a semiconductor substrate. A first etch mask is formed over the lower dielectric layer and is patterned using a reticle. A first etch is applied through an opening in the first etch mask to form an opening in the lower dielectric layer. A lower conductor is formed in the opening in the lower dielectric layer. A conducting layer is formed over the lower dielectric layer and the lower conductor. A second etch mask is formed over the conducting layer and is patterned using the reticle. A second etch is applied through an opening in the second etch mask to form a contact pad from an unetched portion of the conducting layer. An upper dielectric layer is formed over the lower dielectric layer and the contact pad. A third etch mask is formed over the upper dielectric layer and is patterned using the reticle.

Abstract: A laminated substrate including a substrate and a hydrophilic resin layer formed on the substrate, wherein the hydrophilic layer is one made from a resin composition including a hydrophobic polymer linked to a hydrophilic polymer having acidic groups, salts of acidic groups, basic groups, or salts of basic groups; a photosensitive lithographic printing plate including a substrate and a dampening water receiving layer and a photosensitive layer formed on the substrate successively, wherein the above hydrophilic resin layer is used as the dampening water receiving layer; and an image-adding lithographic printing plate including a substrate and an image-receiving layer formed on the substrate, wherein the above hydrophilic resin layer is used as the image-receiving layer.

Abstract: An image formation method which comprises: (a) selectively exposing a photosensitive layer with a visible laser beam, (b) heating the exposed photosensitive layer at a temperature of from 36 to 48.degree. C. for 10 seconds to 3 minutes, and (c) developing the photosensitive layer.

Abstract: According to the present invention there is provided a heat mode imaging element comprising in the order given:i) a lithographic base having a hydrophilic surface,ii) a layer comprising a metal and/or a metallic derivative capable of being ablated by actinic radiation andiii) a hydrophobic layercharacterized in that the hydrophobic layer is a cross-linked layer.