Patents Examined by Johannes P. Mondt
  • Patent number: 10147879
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to integrated circuit fabrics including correlated electron switch devices having various impedance characteristics.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 4, 2018
    Assignee: ARM Ltd.
    Inventor: Lucian Shifren
  • Patent number: 10128262
    Abstract: An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Randy J. Koval, Hiroyuki Sanda
  • Patent number: 10115900
    Abstract: Various materials can be deposited on an OLED substrate at various steps, in which the materials may subsequently require drying, baking and a combination thereof. Given the critical nature of drying and baking steps, the inventors of the present teachings have designed various modules for carrying out drying and baking which can be used as a process development module, and additionally for as a dedicated process module in production.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: October 30, 2018
    Assignee: Kateeva, Inc.
    Inventors: Conor F. Madigan, Eliyahu Vronsky, Alexander Sou-Kang Ko
  • Patent number: 10062840
    Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Rie Sim, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10056524
    Abstract: A semiconductor light-emitting element includes: a first semiconductor layer of a first conductivity type; a light-emitting functional layer including a light emitting layer formed on the first semiconductor layer; and a second semiconductor layer that is formed on the light-emitting functional layer and of a conductivity type opposite to the conductivity type of the first semiconductor layer. The light-emitting layer has: a base layer that has a composition subject to stress strain from the first semiconductor layer and a plurality of base segments formed in a random net shape; and a quantum well structure layer formed by embedding the base layer and composed of at least one quantum well layer and at least one barrier layer. The base layer has a plurality of sub-base layers composed of AlGaN with different Al compositions.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 21, 2018
    Assignees: STANLEY ELECTRIC CO., LTD., THE UNIVERSITY OF TOKYO
    Inventors: Hiroyuki Togawa, Masakazu Sugiyama, Mathew Manish
  • Patent number: 10044002
    Abstract: A display device includes a display panel and a camera module. The display panel displays an image on a first surface, and includes a first substrate, a sub-pixel structure, a reflection pattern, and a transflective reflection pattern. The first substrate included a plurality of pixel regions each having sub-pixel regions, a transparent region, and a reflection region surrounding the sub-pixel regions and the transparent region. The second substrate is disposed on the sub-pixel structure. The reflection pattern is disposed in the reflection region on the second substrate, and exposes the sub-pixel regions and the transparent region. The transflective reflection pattern is disposed on the second substrate, and has an opening exposing at least a portion of at least one transparent region among the transparent regions. The camera module is disposed in the second surface on the display panel, and the second surface is opposite to the first surface.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dae-Woo Lee, Shin-Moon Kang, Byoung-Ki Kim, Hee-Kyung Kim, Hyun-Chul Son, Ji-Hoon Song, Yeon-Sung Lee, Yun-Mo Chung
  • Patent number: 10038029
    Abstract: A light-emitting device includes a growth substrate, a plurality of light-emitting diode units formed on the growth substrate and arranged in a closed loop, an electrode directly formed on the growth substrate, an electrical connection structure formed on the growth substrate and connecting the plurality of light-emitting diode units with the electrode, and a plurality of rectifying diodes connecting to respective nodes of the closed loop.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 31, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Schang-Jing Hon, Alexander Chan Wang, Li-Tian Liang, Chin-Yung Fan, Chien-Kai Chung, Min-Hsun Hsieh
  • Patent number: 10038009
    Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Sung Lim, Jang-Gn Yun, Jaesun Yun
  • Patent number: 10032674
    Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Balasubramanian Pranatharthiharan
  • Patent number: 10008620
    Abstract: The method of making a gallium antimonide near infrared photodetector is a physical vapor deposition-based method of forming a thin film of gallium antimonide (GaSb) on a mica substrate for use as a photodetector for light in the near infrared range. Following physical vapor deposition (PVD) of the thin film of GaSb on the mica substrate, a pair of spaced apart electrodes is attached to the thin film of GaSb, thus forming the gallium antimonide near infrared photodetector.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED ARAB EMIRATES UNIVERSITY
    Inventors: Adel Najar, Muhammad Shafa
  • Patent number: 10002794
    Abstract: Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 19, 2018
    Assignee: International Business Machines
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9997687
    Abstract: A light-emitting device comprising: a supportive substrate; a transparent layer formed on the supportive substrate, and the transparent layer comprising conductive metal oxide material; a light-emitting stacked layer comprising an active layer formed on the transparent layer; and an etching-stop layer formed between the light-emitting stacked layer and the supportive substrate and contacting the transparent layer, wherein a thickness of the etching-stop layer is thicker than that of the transparent layer.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: June 12, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-I Chen, Chia-Liang Hsu, Tzu-Chieh Hsu, Han-Min Wu, Ye-Ming Hsu, Chien-Fu Huang, Chao-Hsing Chen, Chiu-Lin Yao, Hsin-Mao Liu, Chien-Kai Chung
  • Patent number: 9985254
    Abstract: A manufacturing method of a display device is provided. The manufacturing method includes: forming a first electrode over a substrate; forming an organic layer over the first electrode; and forming a second electrode over the organic layer by sputtering a target including a conductive oxide with a light-transmitting property. A mask is arranged between the organic layer and the target when the second electrode is formed. The mask has periodically arranged through holes with a maximum width equal to or larger than 0.1 ?m and equal to or smaller than 3 ?m.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 29, 2018
    Assignee: Japan Display Inc.
    Inventor: Keisuke Ono
  • Patent number: 9978621
    Abstract: Embodiments include a real time etch rate sensor and methods of for using a real time etch rate sensor. In an embodiment, the real time etch rate sensor includes a resonant system and a conductive housing. The resonant system may include a resonating body, a first electrode formed over a first surface of the resonating body, a second electrode formed over a second surface of the resonating body, and a sacrificial layer formed over the first electrode. In an embodiment, at least a portion of the first electrode is not covered by the sacrificial layer. In an embodiment, the conductive housing may secure the resonant system. Additionally, the conductive housing contacts the first electrode, and at least a portion of an interior edge of the conductive housing may be spaced away from the sacrificial layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 22, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Philip Allan Kraus, Timothy Joseph Franklin
  • Patent number: 9969614
    Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 9960091
    Abstract: A package includes: a semiconductor element; a case having an opening and housing the semiconductor element; and a lid having a rectangular parallelepiped shape and occluding the opening of the case. In the package, the lid is joined to an end portion of the opening of the case, and includes a bent portion surrounded by a portion joining the lid to the case and extending along a longitudinal side of the lid.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 1, 2018
    Assignees: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Tomohiro Mitani, Takashi Uchida, Georg Refcio
  • Patent number: 9960197
    Abstract: Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 1, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Weng-Jin Wu
  • Patent number: 9954013
    Abstract: This invention aims at reducing the probability of short-circuiting between terminals in a display device in which an IC driver is connected by COG. Terminals for connection with the IC driver are formed in a terminal region of a TFT substrate (100). The terminals are each comprised of a terminal metal (60), a first through-bole formed in a first insulation film (107), a second through-hole formed in a second insulation film (109), a first ITO (20) formed in the first through-hole and being in contact with the terminal metal (60), and a second ITO (30) formed over the first ITO (20). The second ITO (30) is formed within an area where the second ITO is in contact with the first ITO but is not formed outside the second through-hole. This ensures that the distance between the ITOs of the adjacent terminals can be enlarged, whereby the probability of short-circuiting between the terminals can be lowered.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 24, 2018
    Assignee: Japan Display Inc.
    Inventors: Tomonori Nishino, Syou Yanagisawa, Kentaro Agata, Nobuyuki Ishige
  • Patent number: 9954198
    Abstract: A display device includes a circuit substrate that is formed of a plurality of layers including a light control element; a counter substrate that faces a surface of the circuit substrate on which the light control element is disposed, with a gap therebetween; a seal that is disposed between the circuit substrate and the counter substrate to surround the light control element; and a filler with which a sealed space surrounded by at least the circuit substrate, the counter substrate, and a sealing surface of the seal is filled. The sealing surface includes internal angle corner surfaces formed by an inner surface of the seal, and a convex surface formed adjacent to the corner surfaces from at least one of the circuit substrate, the counter substrate, and the seal.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 24, 2018
    Assignee: Japan Display Inc.
    Inventors: Toshihiro Sato, Tetsuya Nagata, Tohru Sasaki
  • Patent number: 9947553
    Abstract: The present invention provides a semiconductor device and a method for manufacturing a semiconductor device. The method comprises: Preparing a semiconductor chip 6 with a first electrode layer 21 formed on an element-forming surface 7. Prepared a support member 30 having a conductor 31 formed on a pattern-forming surface 33. The first electrode layer 21 is bonded to the conductor 31 by a solder, and thus the semiconductor chip 6 is fixed on the support member 30. While the semiconductor chip 6 is fixed on the support member 30, the semiconductor chip 6 is coated by the sealing resin 3 to form a sealing structure 46. By removing the support member 30 from the sealing structure 46, the conductor 31 formed on the support member 30 is transferred to the sealing structure 46. The conductor 31 transferred to the sealing structure 46 is an external electrode exposed from the sealing structure 46.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 17, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Mamoru Yamagami, Yasuhiro Fuwa