Abstract: A false report on appearance inspection of a semiconductor device is prevented by suppressing variation in surface state of an electrodeposited gold electrode. In formation of an electrodeposited gold electrode, an electrodeposited gold electrode comprised of a plurality of electrodeposited gold layers in the stack is formed by alternately repeating a step of performing energization between an anode electrode and a cathode electrode provided in a treatment cup of a plating apparatus to cause crystal growth of an electrodeposited gold layer (energization ON), and a step of performing no energization between the anode electrode and the cathode electrode (energization OFF). Consequently, even if aging variation occurs in composition of the plating solution, variation in surface state of the electrodeposited gold electrode is suppressed, and a surface state with a surface roughness of, for example, about 0.025 rad can be maintained.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one TS-short-related failure mode.

Abstract: A semiconductor module according to one embodiment of the present invention includes: a first circuit board having thermal conductivity; a second circuit board having thermal conductivity and disposed opposing the first circuit board; a first semiconductor element joined to an opposing surface of the first circuit board opposing the second circuit board; a second semiconductor element joined to an opposing surface of the second circuit board opposing the first circuit board; and a connector electrically connecting the first semiconductor element and the second semiconductor element. The connector includes a portion which is sandwiched between the first semiconductor element and the second circuit board without through the second semiconductor element, and which is in contact with the first semiconductor element and the second circuit board.

Abstract: This invention relates to an optical module package structure. A substrate is defined with a light receiving region and a light emitting region. A light receiving chip and a light emitting chip are disposed on the light receiving region and the light emitting region of the substrate, respectively. An electronic unit is disposed on the substrate and electrically connected to the light emitting chip. Two encapsulating gels are coated on each of the chips and the electronic unit. A cover is disposed on the substrate and has a light emitting hole and a light receiving hole, located above the light emitting chip and the light receiving chip, respectively. In this way, the package structure of the optical module of the present invention integrates passive components, functional ICs or dies into a module, and the optical module provides the functions of current limiting or function adjustment.

Abstract: An interposer includes a plurality of first connection electrodes each of which is arranged on either of first- and second-side-surface sides of a first principal surface of a substrate; a plurality of second connection electrodes each of which is arranged on either of first- and second-side-surface sides of a second principal surface of the substrate; and a plurality of third connection electrodes each of which is arranged on either of first and second side surfaces. Each of the first connection electrodes has a first portion located away from an edge of the first principal surface, and a second portion extending from the first portion to the edge and connected to the third connection electrode. Each of the second portion of each first connection electrode and the plurality of third connection electrodes has a width smaller than a width of the first portion of each first connection electrode.

Abstract: Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE.

Abstract: A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar). The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.

Abstract: Embodiments of the present invention disclose an array substrate and a manufacturing method thereof, a display device, which relates to the display field, and can increase transmittance of the product, and also has improvement effect to defects such as crosstalk, flicker, etc. An embodiment of the present invention provides an array substrate, comprising: a substrate, a data line, a gate line, a thin film transistor and a pixel electrode formed on the substrate, the thin film transistor comprises a gate insulating layer, a part of the gate insulating layer corresponding to a light-transmissive area of a pixel is removed.

Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate 12 and multiple photoelectric converters 40 that are formed on the substrate 12, an insulating film 21 forms an embedded element separating unit 19. The element separating unit 19 is configured of an insulating film 20 having a fixed charge that is formed so as to coat the inner wall face of a groove portion 30, within the groove portion 30 which is formed in the depth direction from the light input side of the substrate 12.

Abstract: A light emitter includes a planar supporting surface, a light source positioned on the spreader region, and an encapsulant positioned on the spreader region to surround the light source. Except where constrained by adhesion to the planar supporting surface, the encapsulant is capable of expanding and contracting in response to a change in temperature so that forces caused by differences in the coefficient of thermal expansion between the different components is minimized. One or more reflective elements can be positioned proximate to the light source to increase the light emitting efficiency of the light emitter. The reflective elements can include a reflective layer on the spreader region and/or a reflective layer on a portion of the encapsulant.

Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a polyurethane resin; at least one other resin selected from the group of an ethylene-vinyl acetate copolymer resin, an acrylonitrile resin, and a styrene resin; isobornyl acrylate; and conductive particles.

Abstract: An array substrate includes a first electrode located above a switching element through a first insulating film, a second electrode located above the first electrode through a second insulating film, and a connection portion that is located to pass through the first insulating film, first electrode, and second insulating film and electrically connects a drain electrode of the switching element and the second electrode. The connection portion is disposed in an avoidance region provided by carving out a gate line connected to the switching element.

Abstract: Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.

Abstract: A semiconductor device includes a gate electrode having a first side wall at an end thereof, a gate insulating layer on a top surface and the first side wall of the gate electrode, an oxide semiconductor layer facing the first side wall, the gate insulating layer being between the first side wall and the oxide semiconductor layer, a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate insulating layer and the first insulating layer, a first electrode connected with a first portion of the oxide semiconductor layer, and a second electrode connected with a second portion of the oxide semiconductor layer.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region.

Abstract: A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

Abstract: A liquid crystal display includes: a first insulating substrate; a plurality of color filters positioned on the first insulating substrate; a light blocking member positioned on the plurality of color filters; a second insulating substrate facing the first insulating substrate; and a spacer positioned between the first insulating substrate and the second insulating substrate, wherein the spacer includes a main column spacer and first and second sub-column spacers, and the first and second sub-column spacers are positioned at both sides of the main column spacer.

Abstract: Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films.

Abstract: A pressure sensor using the MEMS device comprises an airtight ring surrounding a chamber defined by the first substrate and the second substrate. The airtight ring extends from the upper surface of the second substrate to the surface between the first substrate and the second substrate and further breaks out the surface. The pressure sensor utilizes the airtight ring to retain the airtightness of the chamber. The manufacture method of the pressure sensor is also disclosed.