Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulation layer separating the conductive via from the interposer; a first electronic component positioned on the second surface and electrically connected to the conductive via; a first conductive element positioned on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally positioned on the first surface of the interposer and on sidewalls of the first conductive element; and a passivation layer positioned on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Abstract: Performance of an electronic device is improved. A substrate for transfer includes a substrate having a surface and made of a visible light transmitting material, and an elastic deformation portion fixed on the surface of the substrate, transmitting visible light, and made of an elastically deformable material. The elastic deformation portion includes a plurality of element holding portions, and a plurality of protrusions arranged at positions not overlapping with the plurality of element holding portions, and protruding higher than the plurality of element holding portions when the surface of the substrate is a reference plane.

Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.

Abstract: The present application provides a bottom layer metal interconnection line structure, at least including a test key and leads connected to the test key; the test key being composed of a plurality of metal lines connected end-to-end; the plurality of metal lines being arranged in the same plane in a winding manner, wherein at least one suspending via structure is provided at each winding point; and two leads are provided and respectively connected to ends of the metal lines located at a head end and a tail end in the test key. The present application increases a maximum root-mean-square current that the winding metal interconnection lines can withstand while improving a heat dissipation problem of the bottom layer metal interconnection lines.

Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.

Abstract: A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure and vertically span substantially the same tiers of the stack structure as the liner structure.

Abstract: A semiconductor structure includes a substrate; a well region disposed in the substrate; first nanostructures suspended over and vertically arranged over the well region; second nanostructures suspended over and vertically arranged over the well region; and a gate structure wrapped around each of the first nanostructures and each of the second nanostructures. The semiconductor structure further includes a first source/drain feature and a second source/drain feature attached to opposite sides of the first nanostructures, wherein each of the first source/drain feature and the second source/drain feature includes a first bottom dielectric layer over the well region and a first doped epitaxial layer over the first bottom dielectric layer; and a third source/drain feature and a fourth source/drain feature attached to opposite sides of the second nanostructures, wherein each of the third source/drain feature and the fourth source/drain feature includes a second doped epitaxial layer over the well region.

Abstract: According to one embodiment, a display device includes first and second lower electrodes, a rib including first and second pixel apertures, a first organic layer, a second organic layer, a first upper electrode, a second upper electrode, and a partition including a lower portion and an upper portion. The partition includes first and second portions. A first height from an upper surface of the first lower electrode overlapping the first pixel aperture to an upper surface of the first portion is different from a second height from an upper surface of the second lower electrode overlapping the second pixel aperture to an upper surface of the second portion.

Abstract: The present disclosure provides a digital isolator structure and a method for forming the same. The method includes: providing a substrate; forming a first electrode plate on a surface of the substrate and forming a dielectric layer on the first electrode plate; etching the dielectric layer until the first electrode plate is exposed to form a deep trench in the dielectric layer; forming a connect layer on a bottom and a side surface of the deep trench and forming an insulating layer on at least a part of a surface of the connect layer; forming a lead-out electrode layer and a second electrode plate on a surface of the dielectric layer. The lead-out electrode layer is also disposed on a top surface of the connect layer. The method can reduce process steps and save cost of conductive materials.

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.

Abstract: Semiconductor devices including a capacitor and methods of fabricating the semiconductor devices are disclosed. A method of fabricating a semiconductor device including a capacitor includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia though the upper layer and into the middle layer, wherein the supervia hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein the supervia forms a second metal surface of the capacitor above the first metal surface.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.

Abstract: The present invention provides a silicon capacitor structure, including a substrate, an interlayer dielectric (ILD) layer on the substrate, a capacitor recess extending from a surface of the ILD layer into the substrate, a capacitor in the capacitor recess, wherein the capacitor includes a bottom electrode on a surface of the capacitor recess, a capacitive dielectric layer on a surface of the bottom electrode, and a top electrode on a surface of the capacitive dielectric layer and filling up the capacitor recess.

Abstract: A semiconductor device may include a gate structure, a channel structure extending through the gate structure, a first hydrogen supply layer disposed on the gate structure, having a first hydrogen concentration, and comprising an oxygen vacancy, and a hydrogen blocking layer disposed on the first hydrogen supply layer and having a second hydrogen concentration lower than the first hydrogen concentration.

Abstract: A method for making a metal-insulator-metal (MIM) capacitors by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein deposited conformal metal forms a via or contact in the via or contact hole; depositing a bottom electrode metal in the tub to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing bottom electrode metal from the bottom electrode to form a dish-shape upper surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings including respective vertical stack of memory elements and a respective vertical semiconductor channel, forming a lateral isolation trench through the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures, depositing a first tungsten layer in the lateral recesses using a first tungsten deposition process in which a fluorine-containing tungsten precursor gas is used as a reactant, and depositing a second tungsten layer on the first tungsten layer in the lateral recesses using a second tungsten deposition process in which a fluorine-free tungsten precursor gas is used as a reactant.

Abstract: A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to reduced resistance between contacts and source/drain epis. According to one embodiment, a semiconductor device can comprise a source/drain region comprising a top portion, a sidewall portion and a bottom portion, a dielectric bar located adjacent to the source/drain region, and a contact in direct contact with the top portion, the sidewall portion and the bottom portion of the source/drain region and with the dielectric bar.