Abstract: A Schottky diode includes an n-type region, an anode disposed on the n-type region, a buried p-type region, and a shallow p-type region. An interface between the anode and the n-type region forms a Schottky barrier. An n-type channel portion of the n-type region is disposed between the buried p-type region and the shallow p-type region. The anode may also contact the annular shallow p-type region. In an annular configuration, the buried p-type region and the shallow p-type region are annular regions, and the n-type region includes a central portion encircled by the annular shallow p-type region and an annular peripheral portion of the n-type region which encircles the annular shallow p-type region. In one application, a buck converter includes the Schottky diode.

Abstract: A semiconductor device includes a first circuit cell having first transistors, and a second circuit cell having second transistors and arranged with the first circuit cell in an X-direction. Each of the first transistors includes first nanostructures vertically stacked from each other. Each of the second transistors includes second nanostructures vertically stacked from each other. A cell pitch of the first circuit cell and a cell pitch of the second circuit cell in a Y-direction are the same. A first pitch of the first nanostructures in the Z-direction and a second pitch of the second nanostructures in the Z-direction are the same. A first thickness of the first nanostructures in the Z-direction is greater than a second thickness of the second nanostructures in the Z-direction. A first width of the first nanostructures in the Y-direction is greater than a second width of the second nanostructures in the Y-direction.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulation layer separating the conductive via from the interposer; a first electronic component positioned on the second surface and electrically connected to the conductive via; a first conductive element positioned on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally positioned on the first surface of the interposer and on sidewalls of the first conductive element; and a passivation layer positioned on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a first substrate having an integrated circuit formed thereon; a second substrate bonded to the first substrate; and a deep trench capacitor formed on the second substrate and electrically connected to the integrated circuit. The deep trench capacitor includes a stack of conductive layers and dielectric layers disposed in deep trenches, and conductive plugs landing on the conductive layers, respectively. Each of the conductive plugs includes a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer. The first, second and third metal layers are different in composition.

Abstract: A structure includes a substrate, a first transistor on the substrate and a second transistor on the substrate. The second transistor is spaced apart from the first transistor by an isolation region. At least one stress-inducing liner is over the first transistor and the second transistor. An opening extends through at least one stress-inducing liner over at least the isolation region, and a dielectric layer is in at least a portion of the opening. The structure allows for local enhanced high-pressure deuterium (HPD) passivation, which increases threshold voltage of the transistors and improves hot carrier injection with no additional masking. A method of forming the structure is also provided.

Abstract: An integrated circuit includes first second metal levels over a semiconductor substrate. A first capacitor electrode in the first metal level has a plurality of first lines. A second capacitor electrode in the first metal level includes a plurality of second lines alternating with the plurality of first metal lines. A third capacitor electrode in the second metal level includes a plurality of third lines. And a fourth capacitor electrode in the second metal level includes a plurality of fourth parallel lines alternating with the plurality of third metal lines. Each of the third lines is located over a first one of the first lines and a first one of the second lines, and each of the fourth lines is located over a second one of the first lines and a second one of the second lines.

Abstract: A capacitor structure is provided. The capacitor structure includes a substrate, a first electrode, a second electrode, and a third electrode. The first electrode is in the substrate. The second electrode is over the substrate. The third electrode is over the second electrode and includes a middle portion over the second electrode and end portions laterally adjacent to the second electrode.

Abstract: A semiconductor device may include first and second active patterns, first and second gate structures, a source/drain layer, a bit line structure, a contact plug structure, and a capacitor. The first and second active patterns are on a cell region and a peripheral circuit region of a substrate, respectively. The first gate structure extends through an upper portion of the first active pattern. The second gate structure is on an upper surface and an upper sidewall of the second active pattern. The source/drain layer is on a portion of the second active pattern that is adjacent to the second gate structure. The bit line structure is on a central portion of the first active pattern, and overlaps the second gate structure in a horizontal direction. The contact plug structure is on opposing end portions of the first active pattern. The capacitor is on the contact plug structure.

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus.

Abstract: A light-emitting unit includes a substrate, a light-emitting element, and a micro lens. The light-emitting element is disposed on the substrate. The micro lens surrounds the light-emitting element. The micro lens includes compound eye structures adjacent to each other. In a top view, each compound eye structure has a length and a width, and the light-emitting element has a length and a width. The length and width of each compound eye structure in the top view and the length and width of the light-emitting element in the top view substantially satisfy 1?(L1/W1)/(L2/W2)?1.5, in which W1 is the width of the light-emitting element in the top view, L1 is the length of the light-emitting element in the top view, W2 is the width of each compound eye structure in the top view, and L2 is the length of each compound eye structure in the top view.

Abstract: According to one embodiment, a semiconductor device includes: a first substrate; a first transistor provided on the first substrate; a light receiving element; and a light emitting element provided on the light receiving element, wherein the first substrate, the first transistor, the light emitting element, and the light receiving element are disposed sequentially in a first direction.

Abstract: A semiconductor structure includes a substrate; and a buffer layer and a heterojunction structure layer which are disposed on the substrate sequentially, along a direction perpendicular to a direction from the substrate to the buffer layer, the buffer layer includes a plurality of ion implanted regions disposed at intervals, and the plurality of ion implanted regions include an impurity ion. The impurity ion is implanted into the buffer layer at intervals, so that different threshold voltages are formed at the heterojunction structure layer located at different positions in the buffer layer, which makes devices open gradually in a width direction of channels, to relieve decrease of a trans-conductance curve at a relatively large drain current, improving trans-conductance flatness of the devices, and further improving linearity of the devices.

Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

Abstract: A display device includes a substrate including a first display area, and a second display area surrounding at least a part of the first display area in plan view, a first pixel portion in the first display area, a first pixel circuit portion in the first display area, and electrically connected to the first pixel portion, a circuit-driving portion in the second display area, and configured to drive the first pixel circuit portion, a second pixel portion in the second display area to overlap the circuit-driving portion, a second pixel circuit portion in the second display area, and electrically connected to the second pixel portion, and a light-sensing region in the second display area to overlap an electronic component.

Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.

Abstract: A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.

Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, a fin-shaped pattern on a first surface of the back wiring line, a field insulating film disposed on the fin-shaped pattern, a source/drain pattern on the fin-shaped pattern, a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern and a contact connecting via connecting the back wiring line and the source/drain contact, and is in contact with the back wiring line. The contact connecting via includes a first surface connected to the source/drain contact, and a second surface contacted to the back wiring line. A height from a second surface of the back wiring line to an upper surface of the field insulating film is smaller than a height from the second surface of the back wiring line to the first surface of the contact connecting via.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulation layer separating the conductive via from the interposer; a first electronic component positioned on the second surface and electrically connected to the conductive via; a first conductive element positioned on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally positioned on the first surface of the interposer and on sidewalls of the first conductive element; and a passivation layer positioned on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Abstract: Performance of an electronic device is improved. A substrate for transfer includes a substrate having a surface and made of a visible light transmitting material, and an elastic deformation portion fixed on the surface of the substrate, transmitting visible light, and made of an elastically deformable material. The elastic deformation portion includes a plurality of element holding portions, and a plurality of protrusions arranged at positions not overlapping with the plurality of element holding portions, and protruding higher than the plurality of element holding portions when the surface of the substrate is a reference plane.

Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.