Abstract: A semiconductor device is provided. The semiconductor device includes a functional circuit; a plurality of electrostatic discharge (ESD) protection circuits formed independently of the functional circuit, wherein each of the plurality of ESD protection circuits includes a plurality of junctions having different sizes and capacities, each of the plurality of ESD protection circuits is configured to perform an ESD test in different processes of fabrication of the semiconductor device; and a plurality of test pads connected to the plurality of ESD protection circuits and the functional circuit, respectively, wherein each of the plurality of test pads is configured to receive a test signal for the ESD test.
Abstract: Disclosed are embodiments of a back end of the line (BEOL) metal structure that includes, within a metal level, a metal via, which has at least eight sides and all interior angles at 135° or more, and a metal wire thereon. The metal wire and via include respective portions of a continuous conformal metal layer. A passivation layer coats the top surface of the metal layer. The metal via and the metal wire thereon can be in an upper metal level and can be made of one metal (e.g., aluminum or an aluminum alloy). The upper metal level can be above a lower metal level that similarly includes a metal via and metal wire thereon, but the metal used can be different (e.g., copper) and/or the shape of the via can be different (e.g., four-sided). Also disclosed herein are method embodiments for forming the above-described BEOL metal structure.
October 16, 2019
Date of Patent:
September 21, 2021
GlobalFoundries U.S. Inc.
Dirk Breuer, Oliver M. Witnik, Carla Byloos, Holger S. Schuehrer
Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.
Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
April 23, 2019
Date of Patent:
September 14, 2021
Kangguo Cheng, Julien Frougier, Nicolas Loubet
Abstract: Disclosures of the present invention describe a halide semiconductor memristor that is suitable for being as an artificial synapse. The halide semiconductor memristor comprises a first electrode layer, an active layer and a second electrode layer, wherein the active layer comprises a first oxide semiconductor film formed on the first electrode layer, a halide semiconductor film formed on the first oxide semiconductor film, and a second oxide semiconductor film formed on the halide semiconductor film Moreover, a variety of experimental data have proved that, this halide semiconductor memristor is indeed suitable for being adopted as a plurality of artificial synapses that are used in manufacture of a neuromorphic device, and exhibits many advantages, including: capable of being driven by a low operation voltage, having a multi-stage adjustable resistance state, and a wide dynamic range of the switching resistance states.
Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.
Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.
September 20, 2019
Date of Patent:
August 17, 2021
Rishabh Mehandru, Szuya S. Liao, Stephen M. Cea
Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.
Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.
Abstract: The reliability of the semiconductor device is suppressed from deteriorating. A first gate electrode is formed on the semiconductor layer SM located in the SOI region 1A of the substrate 1 having the semiconductor base material SB, the insulating layer BX, and the semiconductor layer SM via the first gate insulating film, a second gate electrode is formed on the semiconductor base material SB located in the first region 1Ba of the bulk region 1B and on which the epitaxial growth treatment is performed via the second gate insulating film, and a third gate electrode is formed on the semiconductor base material SB located in the second region 1Bb of the bulk region 1B and on which the epitaxial growth treatment is not performed via the third gate insulating film.
Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.
Abstract: An infrared detector and a method for manufacturing it are disclosed. The infrared detector contains an absorber layer responsive to infrared light, a barrier layer disposed on the absorber layer, a plurality of contact structures disposed on the barrier layer; and an oxide layer disposed above the barrier layer and between the plurality of the contact structures, wherein the oxide layer reduces the dark current in the infrared detector. The method disclosed teaches how to manufacture the infrared detector.
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.
November 15, 2019
Date of Patent:
June 22, 2021
GLOBALFOUNDRIES U.S. INC.
Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Lars W. Liebmann, Gregory A. Northrop
Abstract: A semiconductor memory device includes a substrate including a cell region on which memory sells are disposed and a connection region on which conductive patterns are disposed, the conductive patterns electrically connected to the memory cells; a first word line stack including a plurality of first word lines that are stacked on the substrate in the cell region and extend to the connection region; a second word line stack including a plurality of second word lines that are stacked on the substrate in the cell region and extend to the connection region, the second word line stack being adjacent to the first word line stack; vertical channels disposed on the cell region of the substrate, the vertical channels being connected to the substrate and respectively coupled with the plurality of first and second word lines; a bridge connecting one of the plurality of first word lines in the first word line stack to a corresponding word line of the second word line stack.
Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
Abstract: A manufacturing method of a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.
Abstract: An off chip driver structure includes a plurality of pull-up transistors, a plurality of pull-down transistors, a plurality of first regions of a first type, a plurality of second regions of a second type and a plurality of resistor components. The first regions and the second regions are staggered to form an electrostatic discharge (ESD) component. One of the resistor components is coupled to one of the pull-up transistors or one of the pull-down transistors, the resistor components are arranged between the first regions and the second regions.
Abstract: A first dummy gate and a second dummy gate are formed on a substrate with a gap between the first and second dummy gates. The first dummy gate has a first sidewall. The second dummy gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second dummy gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.