Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Abstract: A semiconductor structure includes a first dielectric layer, a conductive layer over the first dielectric layer, and a first electrode over a first portion of the conductive layer. A first thickness of the first portion of the conductive layer is greater than a second thickness of a second portion of the conductive layer not under the first electrode.

Abstract: A semiconductor device and a fabrication method of the semiconductor device are provided. The semiconductor device includes a substrate, a source-drain plug layer in the substrate, a gate structure in the substrate, and a dielectric layer disposed over the substrate and covering the gate structure and the source-drain plug layer. The dielectric layer contains a first through-hole having a bottom exposing a top surface of the source-drain plug layer, and a second through-hole having a bottom exposing a top surface of the gate structure. Further, the semiconductor device includes an interface layer disposed on each of the top surface of the source-drain plug layer exposed by the first through-hole and the top surface of the gate structure exposed by the second through-hole.

Abstract: The present invention is directed to III-V semiconductor trench MOSFETs comprising a buried field shield. The invention is further directed to an etch and regrowth method for forming this buried field shield. For example, in III-V trench MOSFETs with an n-type substrate, the region can be formed by an etch into the drift (n-type) and regrowth of p-type semiconductor to form the buried field shield in the trench area and a body/channel outside the trench area. With a narrow trench feature size, the regrowth will planarize enabling subsequent source epitaxy (n-type) without requiring ex-situ processing between body/channel and source growths, eliminating the need for additional masking of the regrowth.

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

Abstract: A semiconductor device includes a source region, a drain region, and a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region to a portion of an upper surface of the gate electrode; a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region; and a gate silicide layer formed between the first dielectric pattern and the spacer.

Abstract: A semiconductor module includes a resin molded part encapsulating a semiconductor chip, a first terminal having a plate shape, and a second terminal having a plate shape. The first terminal and the second terminal are disposed on top of the other in a thickness direction. The first terminal is exposed from a first surface of the resin molded part, and the second terminal is projected from a second surface of the resin molded part to an outside of the resin molded part, the second surface being different from the first surface from which the first terminal is exposed.

Abstract: A method and apparatus for growing an oxide layer within a feature of a substrate is described herein. The method is suitable for use in semiconductor manufacturing. The oxide layer is formed by exposing a substrate to both a high pressure oxidant exposure and a lower pressure oxygen containing plasma exposure. The high pressure oxidant exposure is performed at a pressure of greater than 10 Torr, while the lower pressure oxygen containing plasma exposure is performed at a pressure of less than about 10 Torr. The features are high-aspect ratio trenches or holes within a stack of silicon oxide and silicon nitride layers.

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.

Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

Abstract: A display device is provided. A display device including a plurality of light-output areas through which incident light is emitted and a light-blocking area which blocks the incident light, the display device includes a substrate, a bank layer which is disposed in the light-blocking area on the substrate and defines a plurality of openings, each of which is disposed in one of the plurality of light-output areas, and a color control pattern disposed in the opening of the bank layer, wherein the bank layer includes a first bank area which has a first thickness and defines the plurality of openings and a second bank area which is disposed between the plurality of openings and has a second thickness smaller than the first thickness.

Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Abstract: A display device includes a first electrode, second electrodes, light emitting elements, a bank layer, and connection electrodes. Each of the second electrodes comprises an electrode stem part overlapping the bank layer and electrode branch parts branching from the electrode stem part and disposed partially in an emission area, and the connection electrodes comprise a first connection electrode disposed on the first electrode, overlapping an upper bank part of the bank layer and having a part disposed in a first sub-area, a second connection electrode disposed on a first electrode branch part of one of the second electrodes, overlapping a lower bank part of the bank layer and having a part disposed in a second sub-area, and a third connection electrode disposed on second electrode branch parts of different second electrodes of the second electrodes and on the first electrode and surrounding a part of the first connection electrode.

Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.

Abstract: Disclosed is a bi-directional two-terminal phase-change memory device using a tunneling thin film and a method of operating the same. According to an one embodiment, a phase-change memory device comprises: a first electrode; a second electrode; and a phase-change memory cell interposed between the first electrode and the second electrode, wherein the phase-change memory cell comprises: a P-type intermediate layer used as a data storage as a crystal state changes due to a voltage applied through the first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling thin film disposed on at least one area from among an area between the upper layer and the intermediate layer or an area between the lower layer and the intermediate layer, so as to reduce a leakage current in the intermediate layer or prevent intermixing between a P-type dopant and an N-type dopant.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Abstract: Gas sensors having laser-induced graphene (LIG) and/or LIG composites, and methods of making and using gas sensors having LIG and/or LIG composites.

Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided. A lower electrode is formed on the substrate. A capacitor dielectric layer is formed on a surface of the lower electrode. The capacitor dielectric layer includes at least one zirconium oxide layer. The capacitor dielectric layer is subjected with microwave annealing treatment to convert a crystal phase of zirconium oxide to a tetragonal crystal phase. An upper electrode is formed on a surface of the capacitor dielectric layer.