Abstract: A display panel includes a display area and a non-display area disposed on at least one side of the display area, and further includes an array substrate, a first optical structure layer, and a second optical structure. The first optical structure layer is provided with a plurality of pixel openings, grooves, and dams. The dams and the grooves intersect with an edge of the non-display area at an included angle, and the included angle is 80° to 100°.

Abstract: Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system.

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of interleaved conductive layers and dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and having a plurality of protruding portions abutting the conductive layers and a plurality of normal portions abutting the dielectric layers. Each of the plurality of channel structures includes a blocking layer along a sidewall of the channel structure, and a storage layer over the blocking layer. The storage layer includes a plurality of charge trapping structures in the protruding portions of the channel structure, and a plurality of protecting structures in the normal portions of the channel structure and connecting the plurality of charge trapping structures.

Abstract: A method for manufacturing a capacitor structure is provided. A substrate having a first side and a second side opposite to the first side is provided. A plurality of first trenches are formed on the first side. A first capacitor is formed extending along the first side and into the first trenches. A plurality of second trenches are formed on the second side. A second capacitor is formed extending along the second side and into the second trenches.

Abstract: Provided is an image sensor including a substrate, in which a pixel area including a plurality of unit pixels, an optical black area located outside of the pixel area, and an alignment key area located outside of the pixel area are included, the substrate having a first surface and a second surface opposing the first surface, an interconnection structure below the first surface of the substrate, photoelectric conversion elements in the pixel area of the substrate, an insulating layer on the second surface of the substrate, a grid layer on the insulating layer in the pixel area and the alignment key area, a key pattern layer between the insulating layer disposed in the alignment key area and the grid layer disposed in the alignment key area, the key pattern layer including a protruding region to correspond to the grid layer, and color filters on the insulating layer and the grid layer in the pixel area.

Abstract: A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.

Abstract: The present disclosure provides an improved field effect transistor and device that can be used to sense and characterize a variety of materials. The field effect transistor and/or device including the transistor may be used for a variety of applications, including genome sequencing, protein sequencing, biomolecular sequencing, and detection of ions, molecules, chemicals, biomolecules, metal atoms, polymers, nanoparticles and the like.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.

Abstract: A nick is disposed in a display region so as to partly cut the display region. A first routed wire is routed from the display region toward the nick. The first routed wire is included in a first metal layer. A first conductive film is included in a second metal layer. The first routed wire and the first conductive film overlap each other via an inorganic insulating film.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: A semiconductor device includes a first well region in a substrate; a first dielectric layer over the first well region, wherein the first dielectric layer includes a stepped shape over the first well region; and a conductive layer over the first well region. The conductive layer forms a Schottky barrier interface with the first well region.

Abstract: A display device is provided with a first adhesive layer formed on a sealing layer in a display region and a flexible sheet formed on a resin layer on an opposite side of a TFT layer, in which a first inorganic insulating layer has a first slit, the flexible sheet has a second slit, and the first adhesive layer is formed in a state of extending from the display region to a frame region, and overlapping with the first slit and the second slit.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.