Patents Examined by John A Bodnar
  • Patent number: 11903272
    Abstract: A display substrate includes a plurality of data lines and a plurality of columns of pixel driving circuits. A column of pixel driving circuits is connected to a corresponding data line, and each pixel driving circuit includes a driving transistor and a first transistor. The driving transistor is a P-type transistor. The first transistor includes: a first active pattern having a first channel region, and a first doped region and a second doped region on two opposite sides of the first channel region; a first gate; and a first insulating block disposed on a side of the first active pattern away from the base and having a first via. The data line is connected to a portion of the first active pattern located in the first doped region through the first via. Sizes of all first vias in the column of pixel driving circuits gradually decrease in a first direction.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: February 13, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Honghao Zhao, Wenjun Liao, Yanting Lu, Taoran Zhang, Da Zhou, Jianbo Wang, Wenjin Huang
  • Patent number: 11903212
    Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventor: Kyungmin Jang
  • Patent number: 11901240
    Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeonghyuk Yim, Kang Ill Seo
  • Patent number: 11901364
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11894308
    Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
  • Patent number: 11894373
    Abstract: A semiconductor device includes a substrate, a first transistor and a second transistor disposed on the substrate, and a first contact structure. The first transistor includes first semiconductor channel layers stacked and separated from one another, and a first source/drain structure and a second source/drain structure disposed at two opposite sides of and connected with each first semiconductor channel layer. The second transistor includes second semiconductor channel layers disposed above the first semiconductor channel layers, stacked, and separated from one another, and a third source/drain structure and a fourth source/drain structure disposed at two opposite sides of and connected with each second semiconductor channel layer. The first contact structure penetrates through the third source/drain structure.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11887838
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Anthony St. Amour, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11881442
    Abstract: Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 23, 2024
    Assignee: Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd.
    Inventors: Bao Zhu, Lin Chen, Qingqing Sun, Wei Zhang
  • Patent number: 11875993
    Abstract: A method of fan-out processing includes providing or obtaining a fused glass laminate sheet or wafer having a core layer and a first clad layer and a second clad layer, the core layer comprising a core glass having a core glass coefficient of thermal expansion ?core, the first clad layer and the second clad layer each comprising a clad glass having a clad glass coefficient of thermal expansion ?clad, where ?clad>?core; affixing integrated circuit devices to the second clad layer of the laminate sheet or wafer; forming a fan-out layer on or above the integrated circuit devices; and removing some of the first clad layer to decrease warp of the sheet or wafer with integrated circuit devices and a fan-out layer thereon. A method of producing a laminate sheet or wafer having a selected CTE is also disclosed.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: January 16, 2024
    Assignee: CORNING INCORPORATED
    Inventors: Jin Su Kim, Yu Xiao
  • Patent number: 11862719
    Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 2, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Saptharishi Sriram, Thomas Smith, Alexander Suvorov, Christer Hallin
  • Patent number: 11855086
    Abstract: A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Shao Cheng, Chui-Ya Peng, Kung-Wei Lee, Shin-Yeu Tsai
  • Patent number: 11854834
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11855078
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11854800
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Patent number: 11854822
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Patent number: 11855085
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Patent number: 11848391
    Abstract: An infrared detector and a method for manufacturing it are disclosed. The infrared detector contains an absorber layer responsive to infrared light, a barrier layer disposed on the absorber layer, a plurality of contact structures disposed on the barrier layer; and an oxide layer disposed above the barrier layer and between the plurality of the contact structures, wherein the oxide layer reduces the dark current in the infrared detector. The method disclosed teaches how to manufacture the infrared detector.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: December 19, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventor: Pierre-Yves Delaunay
  • Patent number: 11843001
    Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: December 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byounghak Hong, Seunghyun Song, Ki-Il Kim, Gunho Jo, Kang-Ill Seo
  • Patent number: 11837456
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Heidi M. Meyer, Ahmet Tura, Byron Ho, Subhash Joshi, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11837643
    Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.
    Type: Grant
    Filed: March 14, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien Hung Liu