Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus.

Abstract: A light-emitting unit includes a substrate, a light-emitting element, and a micro lens. The light-emitting element is disposed on the substrate. The micro lens surrounds the light-emitting element. The micro lens includes compound eye structures adjacent to each other. In a top view, each compound eye structure has a length and a width, and the light-emitting element has a length and a width. The length and width of each compound eye structure in the top view and the length and width of the light-emitting element in the top view substantially satisfy 1?(L1/W1)/(L2/W2)?1.5, in which W1 is the width of the light-emitting element in the top view, L1 is the length of the light-emitting element in the top view, W2 is the width of each compound eye structure in the top view, and L2 is the length of each compound eye structure in the top view.

Abstract: According to one embodiment, a semiconductor device includes: a first substrate; a first transistor provided on the first substrate; a light receiving element; and a light emitting element provided on the light receiving element, wherein the first substrate, the first transistor, the light emitting element, and the light receiving element are disposed sequentially in a first direction.

Abstract: A semiconductor structure includes a substrate; and a buffer layer and a heterojunction structure layer which are disposed on the substrate sequentially, along a direction perpendicular to a direction from the substrate to the buffer layer, the buffer layer includes a plurality of ion implanted regions disposed at intervals, and the plurality of ion implanted regions include an impurity ion. The impurity ion is implanted into the buffer layer at intervals, so that different threshold voltages are formed at the heterojunction structure layer located at different positions in the buffer layer, which makes devices open gradually in a width direction of channels, to relieve decrease of a trans-conductance curve at a relatively large drain current, improving trans-conductance flatness of the devices, and further improving linearity of the devices.

Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

Abstract: A display device includes a substrate including a first display area, and a second display area surrounding at least a part of the first display area in plan view, a first pixel portion in the first display area, a first pixel circuit portion in the first display area, and electrically connected to the first pixel portion, a circuit-driving portion in the second display area, and configured to drive the first pixel circuit portion, a second pixel portion in the second display area to overlap the circuit-driving portion, a second pixel circuit portion in the second display area, and electrically connected to the second pixel portion, and a light-sensing region in the second display area to overlap an electronic component.

Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.

Abstract: A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.

Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, a fin-shaped pattern on a first surface of the back wiring line, a field insulating film disposed on the fin-shaped pattern, a source/drain pattern on the fin-shaped pattern, a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern and a contact connecting via connecting the back wiring line and the source/drain contact, and is in contact with the back wiring line. The contact connecting via includes a first surface connected to the source/drain contact, and a second surface contacted to the back wiring line. A height from a second surface of the back wiring line to an upper surface of the field insulating film is smaller than a height from the second surface of the back wiring line to the first surface of the contact connecting via.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulation layer separating the conductive via from the interposer; a first electronic component positioned on the second surface and electrically connected to the conductive via; a first conductive element positioned on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally positioned on the first surface of the interposer and on sidewalls of the first conductive element; and a passivation layer positioned on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Abstract: Performance of an electronic device is improved. A substrate for transfer includes a substrate having a surface and made of a visible light transmitting material, and an elastic deformation portion fixed on the surface of the substrate, transmitting visible light, and made of an elastically deformable material. The elastic deformation portion includes a plurality of element holding portions, and a plurality of protrusions arranged at positions not overlapping with the plurality of element holding portions, and protruding higher than the plurality of element holding portions when the surface of the substrate is a reference plane.

Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.

Abstract: The present application provides a bottom layer metal interconnection line structure, at least including a test key and leads connected to the test key; the test key being composed of a plurality of metal lines connected end-to-end; the plurality of metal lines being arranged in the same plane in a winding manner, wherein at least one suspending via structure is provided at each winding point; and two leads are provided and respectively connected to ends of the metal lines located at a head end and a tail end in the test key. The present application increases a maximum root-mean-square current that the winding metal interconnection lines can withstand while improving a heat dissipation problem of the bottom layer metal interconnection lines.

Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.

Abstract: A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure and vertically span substantially the same tiers of the stack structure as the liner structure.

Abstract: A semiconductor structure includes a substrate; a well region disposed in the substrate; first nanostructures suspended over and vertically arranged over the well region; second nanostructures suspended over and vertically arranged over the well region; and a gate structure wrapped around each of the first nanostructures and each of the second nanostructures. The semiconductor structure further includes a first source/drain feature and a second source/drain feature attached to opposite sides of the first nanostructures, wherein each of the first source/drain feature and the second source/drain feature includes a first bottom dielectric layer over the well region and a first doped epitaxial layer over the first bottom dielectric layer; and a third source/drain feature and a fourth source/drain feature attached to opposite sides of the second nanostructures, wherein each of the third source/drain feature and the fourth source/drain feature includes a second doped epitaxial layer over the well region.

Abstract: According to one embodiment, a display device includes first and second lower electrodes, a rib including first and second pixel apertures, a first organic layer, a second organic layer, a first upper electrode, a second upper electrode, and a partition including a lower portion and an upper portion. The partition includes first and second portions. A first height from an upper surface of the first lower electrode overlapping the first pixel aperture to an upper surface of the first portion is different from a second height from an upper surface of the second lower electrode overlapping the second pixel aperture to an upper surface of the second portion.

Abstract: The present disclosure provides a digital isolator structure and a method for forming the same. The method includes: providing a substrate; forming a first electrode plate on a surface of the substrate and forming a dielectric layer on the first electrode plate; etching the dielectric layer until the first electrode plate is exposed to form a deep trench in the dielectric layer; forming a connect layer on a bottom and a side surface of the deep trench and forming an insulating layer on at least a part of a surface of the connect layer; forming a lead-out electrode layer and a second electrode plate on a surface of the dielectric layer. The lead-out electrode layer is also disposed on a top surface of the connect layer. The method can reduce process steps and save cost of conductive materials.