Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Abstract: A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.

Abstract: An infrared detector and a method for manufacturing it are disclosed. The infrared detector contains an absorber layer responsive to infrared light, a barrier layer disposed on the absorber layer, a plurality of contact structures disposed on the barrier layer; and an oxide layer disposed above the barrier layer and between the plurality of the contact structures, wherein the oxide layer reduces the dark current in the infrared detector. The method disclosed teaches how to manufacture the infrared detector.

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

Abstract: There is provided a laminated substrate having a piezoelectric film, including: a substrate; a first electrode film provided on the substrate; and a piezoelectric film provided on the first electrode film, wherein an oxide film containing an oxide represented by a composition formula of RuOx or IrOx, is provided on the piezoelectric film.

Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Abstract: An object of the present invention is to provide a vibration sensor in which the frequency dependence of the output is small. The present invention provides a vibration sensor 1 comprising: a support 2; an organic piezoelectric material 3 deformably disposed in or on the support 2; and an electrode 4 for extracting an electrical signal generated by deformation of the organic piezoelectric material 3, the electrode 4 being formed on the organic piezoelectric material 3, the organic piezoelectric material 3 comprising a copolymer of vinylidene fluoride and one or more monomers copolymerizable with vinylidene fluoride.

Abstract: An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.

Abstract: An energy storage device comprising a substrate comprising a groove having a first and a second face. A capacitor material in the groove. The first and the second face of the groove having a coat of metal. Wherein the coat of metal on the first face is not in electrical contact with the coat of metal on the second face.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.

Abstract: A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.