Abstract: A memory system includes a first volatile memory having an access unit of a first bit width; a second volatile memory having an access unit of the first bit width and having a capacity larger than the first volatile memory; and a controller connected to the first and second volatile memories. The controller allocates a first address space having the first bit width as a unit to the first volatile memory, allocates a second address space having the first bit width as a unit to the second volatile memory, selects at least one of the first and second volatile memories based on a first address indicating a position in a third address space having a second bit width as a unit, calculates a second address in the address space allocated to the selected volatile memory, and accesses a position corresponding to the second address of the selected volatile memory.

Abstract: Methods and systems for solid state drives are provided, including assigning a first namespace to a first instance of a storage operating system and a second instance of the storage operating system for enabling read access to a first portion of a flash storage system by the first instance, and read and write access to the second instance; allocating a second namespace to the first instance for exclusive read and write access within a second portion of the flash storage system; generating, by the first instance, a request for the second instance to transfer a data object from the second portion owned by the first instance to the first portion; storing, by the second instance, the data object at the first portion; and updating metadata of the data object at the second portion, the metadata indicating a storage location at the second portion where the data object is stored.

Abstract: A memory controller that controls a memory device including a plurality of memory blocks allocated to a plurality of zones for storing data is provided. The memory controller comprises a plurality of processing cores controlling data operations in the plurality of zones in the memory device; and an external interface unit in communication with an external device and configured to receive, from the external device, a write request requesting to perform a write operation on a first zone in the memory device, the external interface unit configured to identify a first processing core for controlling the first zone and determine a second core to perform the write operation based on a number of open zones controlled by the first core and having an open state indicating a capability to execute a program operation.

Abstract: A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.

Abstract: A controller of a memory system according to an embodiment manages, for each of a plurality of blocks, first information indicating whether a corresponding block is in use which indicates a state where the data is stored, second information indicating the number of erasures, and third information indicating a waiting time until next erasure. The controller executes first sequential write received from a host, and determines whether to execute processing of leveling the number of erasures for each of the plurality of blocks based on a first difference, a second difference, and a third difference when executing second sequential write received from the host.

Abstract: A data storage system can have one or more hosts connected to a data storage subsystem with the host having a host processor and the data storage subsystem having a controller. Write back data generated at the host triggers the host processor to allocate a cache location in the data storage subsystem where the generated data is subsequently stored. The generated write back data is written in a non-volatile destination address as directed by the controller prior to waiting for a secondary event with the generated data stored in both the cache location and the non-volatile destination address. Detection of the secondary event prompts the controller to signal the host processor that the cache location is free for new data.

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

Abstract: A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.

Abstract: Techniques for persisting user data across secure shell instances are provided. A method includes receiving a first request from a session manager service to establish a connection to a secure shell instance and restore a user block volume with corresponding backup user data. The method may include reserving an empty block volume. The method may also include transmitting a backup data identifier associated with the corresponding backup user data to a backup service and receiving the corresponding backup user data from the backup service. The method may further include providing the corresponding backup user data to the empty block volume to create a restore volume and transmitting a restore volume identifier corresponding to a data center identifier to the session manager service. The method may include receiving a second request to attach the restore volume to a reserved instance, the second request being received from the session manager service.

Abstract: Certain embodiments described herein relate to an improved virtual machine restoration system. In one embodiment, an information management system receives a request to perform a restore of a virtual machine using virtual machine data stored on a secondary storage device. In response, the information management system boots up the virtual machine after restoring only a portion of the virtual machine data that is needed to boot up the virtual machine, thereby reducing latencies associated with virtual machine boot-up. The information management system continues to retrieve additional portions of the virtual machine data from the secondary storage device as such portions are requested by the virtual machine, thereby reducing or minimizing unnecessary data transfer from the secondary storage device.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: A memory system may include a memory controller and a memory device including a plurality of sequential areas. The memory controller may control the performance of a background media scan (BGMS) operation on one or more sequential areas among the plurality of sequential areas. The memory controller may receive an open command for allocating a buffer to a sequential area among the plurality of sequential areas, where first time information corresponds to a time at which the open command is received by the memory controller. The memory controller may calculate a first period based on the first time information, and determine, based on the first period, a skip area in which the BGMS operation is skipped among the plurality of sequential areas for each of a plurality of BGMS periods.

Abstract: An apparatus that includes a processor and a memory. The processor and the memory are configured to provide a first software process configured to execute at a first privilege level; and a second software process configured to execute at a second privilege level, wherein the first privilege level is more restrictive than the second privilege level. The processor is configured to, initialize, at the first privilege level, a memory pool within the memory, allocate, at the first privilege level, a block of memory, send a request to write protect the block of memory to the second software process, and to write protect, at the second privilege level, the allocated block of memory.

Abstract: An information processing apparatus receives an access request to a plurality of storage devices and executes access to one of the plurality of storage devices in response to the received access request. The information processing apparatus changes a mode of the access according to a performance required for readout of target data that is a target of the access request.

Abstract: A method of preserving the contiguity of large pages of a workload during migration of the workload from a source host to a destination host includes the steps of: detecting at the destination host, receipt of a small page of zeros from the source host, wherein, at the source host, the small page is part of one of the large pages of the workload; and upon detecting the receipt of the small page of zeros, storing, at the destination host, all zeros in a small page that is part of one of the large pages of the workload.

Abstract: Methods, apparatuses, and systems related to securing memory data are described. A hardware circuit is configured to encrypt and decrypt memory data using a scrambling key unique to a computing process processing the memory data. In writing the memory data, the hardware circuit generates scrambled memory data based on encrypting the memory data according to the security key. The scrambled memory data is stored for the write operation instead of the memory data. When the same process reads back the scrambled data, the same security key can be used to decrypt the scrambled data and recover the initial unscrambled memory data.

Abstract: The present disclosure provides a method for data storage, a general service entity device, and a storage medium. The method for data storage includes: by adopting a general service entity, receiving data sent by an application entity; performing a lock setting or an overflow setting; selecting a retention strategy for previously stored data according to the lock setting or the overflow setting in the case of satisfying a data overflow condition; and storing part or all of received data according to the retention strategy.

Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.

Abstract: This application discloses a mirrored memory configuration method and apparatus, and a computer storage medium, and belongs to the field of information processing technologies. The method includes the following: After a computer apparatus is started, if the computer apparatus is currently in an OS state and obtains a mirrored memory establishment request, the computer apparatus may switch from the OS state to a BIOS state through system interruption. Then the computer apparatus configures a mirroring relationship in the BIOS state, and switches to the OS state again after configuring the mirroring relationship, to reconfigure a mirrored memory.

Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.