Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: The present invention provides a virtual network, sitting "above" the physical connectivity and thereby providing the administrative controls necessary to link various communication devices via an Access-Method-Independent Exchange. In this sense, the Access-Method-Independent Exchange can be viewed as providing the logical connectivity required. In accordance with the present invention, connectivity is provided by a series of communication primitives designed to work with each of the specific communication devices in use. As new communication devices are developed, primitives can be added to the Access-Method-Independent Exchange to support these new devices without changing the application source code. A Thread Communication Service is provided, along with a Binding Service to link Communication Points. A Thread Directory Service is available, as well as a Broker Service and a Thread Communication Switching Service. Intraprocess, as well as Interprocess, services are available.

Abstract: A panic trap system recovers from inaccurate results produced from out of order execution of instructions in a processor. The panic trap system includes a fetch mechanism (IFETCH) that fetches instructions from an instruction cache. Two queues receive the instructions from the fetch mechanism and execute the instructions out of order. Specifically, an ALU instruction queue (AQUEUE) receives instructions that are directed to the ALU. A memory instruction queue (MQUEUE) receives instructions that are directed to a data cache (DCACHE) or a main memory. The MQUEUE includes instruction registers and corresponding address reorder buffer slots (ARBSLOTs) for receiving memory instructions and data addresses corresponding to the results of instruction execution, respectively. Trap indicator logic is associated with each ARBSLOT for recognizing an architecturally incorrect execution of a memory instruction and for associating a nonarchitectural panic trap indicator with the instruction after execution.

Abstract: A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requester must wait for the data bus to become available and a token passed to the requester. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: In a data gathering/scattering system having a data gathering system and a data scattering system in a parallel computer constituted by a plurality of processors connected in parallel through a common bus or hierarchical common buses, the data gathering/scattering system includes: one processor having a buffer for temporarily storing data gathered from or transmitted to other processors, a three-state buffer for transmitting data from the buffer to the common bus, and a switching unit for switching a connection between a transmission and a reception to form the data gathering system or the data scattering system; each of the other processors having a buffer for temporarily storing data to be transferred or data to be received, a transfer control unit for controlling data transmissions from the buffer to the common bus, a reception control unit for selecting the reception data from among all data on the common bus, a three-state buffer for transmitting data from the buffer to the common bus, and a switching un

Abstract: Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate in MIMD, or SIMD and MIMD in special configurations. In a SIMD array of processors, there is a need to partition the processors into groups related to the type of problem they contain. When the grouping is the result of a computation within the processing element, it is desirable that each processing element be capable of assigning itself to a group, or maybe several groups. This disclosure describes a means of assigning processing elements to groups as an array function conducted in parallel by all active processing elements in the array, and then using grouping to select certain processing elements for a computation that is unique to the group.

Abstract: A coefficient data transfer processing method for a digital signal processor which has a coefficient address pointer independent of a program counter, whereby a processing program and coefficient data are transferred and supplied from a microcomputer determination, whether an instruction is a read instruction of the coefficient data to execute a read cycle steal or with is made; a value of a program counter with is made; when it is the read instruction, new coefficient data is transferred from the microcomputer to a transfer buffer at an instruction read stage and instruction decode stage in a processing unit; and the coefficient data stored in the transfer buffer is written into a coefficient data memory by the read cycle steal at an execute stage in the same processing unit.

Abstract: A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling the operation of the array of processor memory elements. Each of the processor memory elements has a plurality of local autonomous operating modes and is adapted to interpret instructions from the array controller within the processor memory element.

Abstract: A data processing system for determining a matrix of optimal investment portfolios based on globally accessed investment return and risk criteria. The system creates a global defined database of investment assets and investors. Asset and investor characteristics are established and applied to provide solutions to the ensuing linear relationships. These solutions are then individually applied to determine an optimal investment portfolio on an individualized basis.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A bossless computer program architecture in which each program module is hierarchically equal is used to develop complicated software applications. Each program module is associated with a parameter file. The characteristics and operation of the program modules are determined by their associated parameter files. These modules communicate by writing statements to the parameter files associated with other modules. Once written, the origin of these statements is ignored. Thus, there is no need to "return" to the modules which originate the statements. Further, the statements are executed by the modules without regard to their origins. This new architecture does not require the preservation of linkage information because there is no need for the program modules to return information or control to other modules. Various applications of this architecture to windows-based environment and multimedia applications are disclosed.

Abstract: A computer system including separate digital and analog system chips which provides increased performance over current computer architectures. The computer system of the present invention includes a digital system chip which performs various digital functions, including multimedia functions and chipset functions, and a separate analog chip which performs analog functions, including digital to analog and analog to digital conversions. Thus the present invention optimizes silicon use and design by splitting up digital and analog functions on separate chips. The system of the present invention also separates digital noise from analog noise, allowing a higher degree of integration while increasing stability.

Abstract: A method, apparatus, and article of manufacture for establishing an unlimited number of independent, client-based timers, synchronized with a timer kept on a central server, is disclosed. After forming a client-server connection, a client sends a synchronization message to a server. The client receives a return synchronization message from the server, and computes a round-trip interval time between sending and receiving, by sampling a local hardware clock. The sending and receiving of synchronization messages continues for a predetermined number of times, until the client receives a final synchronization message from the server, the final synchronization message including the current local server time. The client then calculates the average one-way trip interval and adds that value to the received current local server time, to provide the client with a reliable estimate of the local server time.

Abstract: A method and system for coupling a coprocessor to a master device, in which the coprocessor emulates an memory interface to the master device, like that of a memory device. The coprocessor is coupled to a memory bus and receives memory accesses directed to a set of addresses not covered by memory devices also coupled to the memory bus. The coprocessor is disposed to receive data written from the master device, perform a coprocessing function on that data, and respond to a read data command from the master device with processing results. The coprocessor uses memory block transfers to read data from and write data to memory devices also coupled to the memory bus. A general purpose computer system comprises a central processor and memory coupled to a PCI bus, a graphics processor and graphics memory coupled to the PCI bus, and a coprocessor coupled to the graphics processor and graphics memory.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. The apparatus includes a Huffman decoder for decoding data words encoded according to the Huffman coding provisions of either H.261, JPEG or MPEG standards. Data words in the tokens include an identifier that identifies the Huffman code standard under which the data words were coded. The Huffman decoder responds to the identifier and converts the received data words to JPEG Huffman coded data words. An index number into a lookup table is associated with each JPEG Huffman coded data word, and a decoded data word is generated corresponding to the index number.

Abstract: A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions.

Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

Abstract: A space vector data path for integrating SIMD scheme into a general-purpose programmable processor. The programmable processor uses a mode field in each instruction to specify, for each instruction, whether an operand is processed in either one of vector or scalar modes. The programmable processor also has a plurality of sub-processing units for receiving the operand and, responsive to an instruction as specified by the mode field in each instruction, for processing the operand in either one of the vector or scalar modes, wherein the vector mode indicates to the plurality of sub-processing units that there are a plurality of elements within the operand and the scalar mode indicates to the plurality of sub-processing units that there is but one element within the operand. For the vector mode, each element is processed by one of the sub-processing units concurrently to generate a vector result.

Abstract: A data processing apparatus capable of receiving a CPU of different data bus widths is disclosed. Terminals for the lower 32 bits of a 64-bit data bus and terminals for upper 32 bits of the 64-bit data bus are provided opposing to one another at a connector. Also, terminals for the lower 3 bits of a byte enable signal and terminals for the upper 4 bits of the byte enable signal are disposed opposing one another. When a first CPU module having a 32-bit CPU is installed, a bus connector board is coupled to the connector to couple the corresponding terminals of the lower 32 bits and the upper 32 bits, and the corresponding terminals of the lower 3 bits and the upper 4 bits of the byte enable signal.