Abstract: Access to data resources on data communications networks is simplified by encoding data resource specifiers into a compressed form which can be stored in a service provider's telephone equipment and transmitted to a user. The service provider stores information objects (e.g., hypertext pages) on one or more host computers at a node of a computer network, and develops compressed, compact resource specifiers for the information objects. A translation of the compressed resource specifier is provided in the user's telephone/terminal device and/or the host computer for translating the compressed resource specifiers back into their uncompressed form. The service provider stores the compressed resource specifiers in his telephone equipment and transmits them to users in response to user requests, such as in DTMF format. A compatible telephone/terminal device at the user's site (e.g., a computer or smartphone) receives and stores the compressed resource specifiers.

Abstract: A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure.

Abstract: A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast translation to a logical address for operation with functional units of microprocessor. Also disclosed is a microprocessor which includes linear tag array and a physical tag array corresponding to the linear tag array, thus allowing the contents of a microprocessor cache to be advantageously monitored from an external bus without slowing the main instruction and data access processing paths.

Abstract: An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.

Abstract: A session recovery mechanism that permits the recovery of a session with a minimal delay to a user and with minimal data loss. When the client/server communications protocol process, such as TCP/IP process, issues an error message to a server and a client, the server and the client switch from a server data socket and a client data socket, respectively, to a new server data socket and a new client data socket, respectively. This switchover is achieved by having the client open a listening socket during its initialization process. Using the client listening socket, the client listens for a connection from the server to switch to a new data socket, in case of, for example, error messages from the TCP/IP process.

Abstract: In submitting each job in a parallel processing system provided with a plurality of processors, execution conditions such as a requested minimum processor number, an upper limit used processor number and a requested execution time are designated for each job and the judgement of whether or not processors equal in number to the requested minimum processor number required by a leading one of execution waiting jobs are in idle states is made for the leading job by use of a table for managing the status of utilization of processors for each job executed and the number of idle processors, a table for managing processors occupied or used by each operating job and a lapse time and a table for managing the execution conditions of each execution waiting job.

Abstract: An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being executed by the microprocessor) to be fetched concurrently. The instruction cache provides an instruction block corresponding to one of the multiple fetch addresses to the instruction processing pipeline of the microprocessor during each consecutive clock cycle, while additional instruction fetch addresses from the predicted instruction stream are fetched. Preferably, the instruction cache includes at least a number of banks equal to the number of clock cycles consumed by an instruction cache access. In this manner, instructions may be provided during each consecutive clock cycle even though instruction cache access time is greater than the clock cycle time of the microprocessor.

Abstract: A packet based data transmission system includes a flexible optimized nonocking transmit interface that incorporates optimized buffer modes, dynamic and static chaining, streaming and the utilization of small packet formats. Static chaining refers to connecting together the linked list for successive packets for the same transmit channel or virtual channel. Dynamic chaining refers to means by which the network interface performs this chaining automatically, thereby solving a blocking problem. On the transmit side, streaming refers to initiating the transmission of packet data before the entire packet data has been presented to the interface. This, in turn, permits more rapid recycling of the buffer space. On the receive side, streaming refers to initiating the processing of packet data before the entire packet has been received.

Abstract: As a method for transferring data between a first data processing apparatus and a second data processing apparatus connected thereto attachably and detachably, there is provided a transmission method of changing protocol having a step for transmitting a first request signal from the first data processing apparatus to the second data processing apparatus, based on a first protocol, for requesting a change from the first protocol to second protocol, a second transmission step for transmitting, when no first response signals to the first request signal are received from the second data processing apparatus, a second request signal to the second data processing apparatus, based on the second protocol, for requesting the change from the first to the second protocol, and a step for determining, in accordance with receiving of a second response signal to the second request signal from the second data processing apparatus, whether data transfer between the apparatuses should be executed or not.

Abstract: A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undelivered requests and unanswered requests. The mechanism regulates congestion on the network by throttling back or ratcheting up the allowed number of undelivered requests and unanswered requests based upon the level of busy and non-busy results of such requests and answers. Congestion is also alleviated by the implementation of a set of large and small send and receive buffers. These buffers are configurably partitioned among virtual I/O channels. Each request virtual I/O channel may utilitize congestion control.

Abstract: A system and method in which remote users may be billed, on a per connection basis, for universal data grade access to their home office servers. Portable device 101 is carried by a transient remote user within wireless range of an Access Point (AP) 110 deployed at, for example, a hotel or airport lounge. Signalling resource 105 inside portable device 101 automatically initiates wireless contact with AP 110. Wireless contact with AP 110 includes a data grade network address of a destination server 130 to which portable device 101 desires to be connected. AP 110 contacts destination server 130, over Internet/data grade WAN 120. Destination server 130 in turn establishes a secure tunnelled Internet Protocol (IP) 124 with portable device 101 through AP 110. Information such as data-rich files or e-mail is then automatically exchanged between destination server 130 and portable device 101.

Abstract: A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract: A power down control mechanism for multiprocessor computer systems. A power down register is maintained for providing a power down control signal to the multiple processing units in the multiprocessing system. Individual processing units can be selectively onlined or offlined as needed. In addition, during system initialization, the power down mechanism of the present invention can be used for onlining additional processors and also used for preventing faulty processors from attempting to become the system's boot system processor.

Abstract: A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.

Abstract: In order to shorten time needed for communication and alleviate the processing load of the handshake procedure, a master CPU and a slave CPU perform an exchange of data utilizing a first data line and a second data line. A key word is entered in a communication message to the master CPU from the slave CPU requesting initialization be performed. An initialization request from the slave CPU to the master CPU is performed with a key word accompanying a communication error from the slave CPU. The master CPU initializes the slave CPU and synchronizes with it by utilizing a request line, and a reply line only when the master CPU power is turned on or when a communication error occurs including the request for initialization by means of the key word.

Abstract: An error checking method and apparatus for appending a variable number of redundancy coding information at the end of each data message or packet transmitted over a multi-stage network for the purpose of protecting the data by using an error detecting code. The amount of additional redundancy coding information implemented is variable and increases with the size of the data message or packet to provide a consistent level of protection.

Abstract: A network element managing system includes a management control section for maintaining and managing network elements such as an exchange or a telecommunication line and a communication control section for controlling the communication processing of the network so that an interface is commonly used between the management control section and the communication control section, thereby satisfying a required performance in both of a processing request relating to maintenance, management and operation and a processing request relating to communication. That is, the system of the invention includes a scheduling section for determining execution order on the basis of the attribute of the processing request, and the loads of the communication control section and the management control section. Also, the communication control section and the management control section have a function for scheduling the processing request on the basis of the attribute of the object to be processed, respectively.

Abstract: A computer system employing an interrupt coprocessor is provided. The interrupt coprocessor is signaled by an interrupt controller to service a particular interrupt request. The interrupt coprocessor may include limited functionality, such that if a particular interrupt request is beyond the capabilities of the interrupt coprocessor, the microprocessor is interrupted. Context saves may be avoided in the interrupt coprocessor. Interrupt latency is reduced, as well as interruption of one or more main microprocessors in the computer system. Several embodiments are shown with a range of interrupt servicing capabilities. A data pump is shown, which is configured to transfer data from a source to a destination. A microcontroller is shown, which may manipulate the data as it is moved from source to destination or access the interrupting device to determine the service needed. Finally, a microprocessor similar to the main microprocessors of the computer system is shown.

Abstract: A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.