Abstract: A Reader/Sorter may have an MICR read head, an OMR read head, and two OCR read heads or a combination thereof.A Reader/Sorter Adapter receives characters read by the Reader/Sorter. The characters include data and formatting symbol characters read from a document and control characters generated by the Reader/Sorter. Certain characters may be identified as queue field identifiers (QFI) by the user via software. These are usually the formatting characters. The control characters are identified as pseudo queue field identifiers (PQFI). QFI and PQFI characters are received by a Multiple Device Controller and allow the firmware to identify the length of the data fields, the head from which the characters were received, and any special conditions associated with reading of a data field.

Abstract: A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus.

Abstract: A data shunting and recovering device is provided to shunt and hold the data stored in a register and its address before writing the register during a delay period following generation of an interrupt. This data is then restored into the register when an instruction of recovering is given. Therefore, it is allowed to achieve the moderating effects of delaying the stopping of the stage advance in data processing upon generation of an instruction for interruption without loss of data stored in the memory prior to writing during this delay period.

Abstract: An execution unit which is part of a general-purpose microprocessor, partitioned between two integrated circuit chips, with the execution unit on one chip and an instruction unit on another chip. The execution unit provides the interface for accessing a main memory to thereby fetch data and macroinstructions for transfer to the instruction unit when requested to do so by the instruction unit. The execution unit receives arithmetic microinstructions in order to perform various arithmetic operations, and receives access-memory microinstructions in order to develop memory references from logical addresses received from the instruction unit. Arithmetic operations are performed by a data manipulation unit which contains registers and arithmetic capability, controlled by a math sequencer.

Abstract: A data processing machine having a device for extending the length of the logic address to (M+N) bits, so that 2.sup.M+N different logic addresses can be formed and become available to the programmer. The original data structure of a computer having a word length of only N bits is then maintained. Programs written for the original machine can be executed without modification. A register bank of a data processing machine having its extension has a first section having a width of N bits which forms the least-significant side or tail, and a second section which has a width of M bits and which forms the more significant side or head. The first section is used in all instructions which utilize an operand from a register or which store an operand in a register, in the same manner as in the computer without the extension.

Abstract: A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.

Abstract: A programmable logic array which uses random-access memories to replace read only memories conventionally used in programmable logic arrays. The programmable logic array includes input and output terminals, an input register connected to the input terminals, an output register connected to the output terminals, first and second random-access memories, addressing means for sequentially and cyclically reading the random-access memories, a buffer register having an input to the output of the second random-access memory and an output connected to the input of the output register, a comparator having a first input connected to the output of the first random-access memory and a second input connected to the output of the input and output registers, the output of the comparator controlling the transfer of the contents of the buffer register and means for resetting the buffer register.

Abstract: An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.

Abstract: An interpretive-type digital data processing system, providing program protection and supporting one or more input high level languages. The system is comprised of a multi-level hierarchy of processors designatable in descending order as S, M, N and P processors is operable so that the processor at each level interprets instructions at the level above in a pipelined manner. Each of the S, M and N processors is provided with its own memory for respectively storing S, M and N instructions which are selected and fetched during system operation so as to provide a hierarchical interpretation of each input high level language. This is accomplished in a manner such that fetched M instructions are first processed by the N-processor in accordance with corresponding fetched N instructions before being employed by the M-processor for processing data.

Abstract: Disclosed is a method and apparatus whereby each time a tape is wound upon a prescribed reel, the winding pattern may be assumed to leave the array of tape-edges in a unique "edge profile" represented by the position of each winding edge as viewed from one side of the reel along a radial direction--this "profile" being interpreted as a "winding signature"; the signature may be detected and recorded in a convenient encoded fashion for possible use in uniquely identifying and documenting each unspooling/rewind sequence to thereby monitor tape use. Illustrative tape is shown wound on a conventional reel, as well as means for detecting the "wrap profile" ("edge profile") of the tape edges on the reel.

Abstract: A relational break signal generating device including two relational comparators which independently compare an address input from a microprocessor to reference addresses previously input thereto and generate output signals which are fed into a combinational logic circuit that produces false and break signals when a prespecified relationship between the input program address and the two reference addresses occurs. The device also includes a circuit for generating pulses each time a break point is detected.

Abstract: Computer and memory system on a wafer which contains redundant elements and which is capable of self-testing and self-configuration to form a complete system consisting of a central processing unit (CPU), a read only memory unit (ROM), and a plurality of read/write random access memory units (RAM). These units are interconnected by a common bus, which is also available for external connections to the wafer. The first CPU tests each ROM to find a good one and then uses the program contained in that ROM to test itself. If the first CPU does not test satisfactorily, the remaining CPU's are tested until a good one is found. The RAM's are then tested with the good ROM and CPU, and the results are tabulated to form a page oriented computer system.

Abstract: Microprocessor apparatus in which the CPU generates as an integral function memory refresh addresses for an external dynamic memory without degradation of CPU performance. The CPU architecture is optimized by dividing the CPU devices selectively into groups during different time periods by the use of switching devices in the internal bus structure.