Patents Examined by John J. Tabone, Jr.
  • Patent number: 10938419
    Abstract: Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a constrained encoding device including a first encoder and a second encoder. The first encoder jointly encodes, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages. The second encoder independently encodes, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Fan Zhang
  • Patent number: 10931306
    Abstract: The disclosure discloses a method and device in UE and a base station for channel coding. A first node first determines a first bit block and then transmits a first radio signal, wherein bits of the first bit block are used to generate bits of a second bit block, a third bit block comprises bits of the second bit block and the first bit block, and the third bit block is used to generate the first radio signal. The first bit block, the second bit block and the third bit block comprise P1, P2 and P3 bits, respectively.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 23, 2021
    Assignee: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventor: Xiaobo Zhang
  • Patent number: 10929226
    Abstract: Providing for increased flexibility for large scale parity, the including: writing data to a storage system, including utilizing a first data protection scheme; identifying, for storage media in the storage system, characteristics of the storage media; identifying, in dependence up the characteristics for the storage media, a second data protection scheme to use for the data; and writing the data to the to the storage system utilizing the second data protection scheme.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 23, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Ethan Miller, Robert Lee, Par Botes, Ronald Karr
  • Patent number: 10930356
    Abstract: The memory controller may include a command generator generating and outputting first and second read commands to a memory device so that respective first and second read operations are performed using a first read voltage, a calculator receiving first and second read data in response to the read commands, comparing the first and second read data each other, and calculating a number of first inverted cells and a number of second inverted cells based on a result of the comparing, each of the first inverted cells having a bit value that inverted from a first bit value to a second bit value, and each of the second inverted cells having a bit value that inverted from the second bit value to the first bit value, and a read voltage determiner changing the first read voltage depending on the number of first inverted cells and the number of second inverted cells.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 10922173
    Abstract: Described are fountain code constructs that solve multiple problems in distributed storage systems by providing systematic encoding, reduced repair locality, reduced encoding/decoding complexity, and enhanced reliability. Embodiments are suitable for the storage of large files and exhibit performance superior to existing codes, and demonstrate reduced implementation complexity and enhanced symbol repair locality.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 16, 2021
    Assignee: Queen's University at Kingston
    Inventors: Toritseju Okpotse, Shahram Yousefi
  • Patent number: 10923212
    Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10910081
    Abstract: Filter information associated with a test to be performed with one or more memory components is determined. A set of memory components matching the filter information may be reserved for use in the testing. Test execution information defining a set of test processes of the test is determined. A connection with a first test process may be established and used to receive feedback information associated with execution of the test process. Based on the feedback information, a failure of the first test process may be identified.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Daniel Scobee, Frederick Jensen
  • Patent number: 10908842
    Abstract: A storage device includes a nonvolatile memory including a plurality of nonvolatile memory cells, a write buffer memory storing first data and second data received from a host, and a storage controller storing the first data and the second data that are stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first program operation and a second program operation on a plurality of first memory cells connected to a first word line group to store the first data, and performs a first program operation and a second program operation on a plurality of second memory cells connected to a second word line group to store the second data. While the storage controller performs the first program operation on the plurality of second memory cells, the first data is written in the write buffer memory.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 2, 2021
    Inventors: Eun Chu Oh, Younggeun Lee, Youngjin Cho, Jin-Hyeok Choi
  • Patent number: 10903936
    Abstract: A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Joong Kim, Seho Myung, Min Jang, Hong-Sil Jeong, Jae-Yoel Kim, Seok-Ki Ahn
  • Patent number: 10903856
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10901033
    Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 26, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10884057
    Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10872009
    Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Patent number: 10866859
    Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 15, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 10868569
    Abstract: Wireless communications systems and methods are introduced. A wireless communication device may arrange a first encoded information block including a first sub-block having a first bit location and a second sub-block having a second bit location. The second bit location is after the first bit location. The wireless communication device may also position the first location earlier in a decoding order of a receiving second wireless communication than the second bit location. The wireless communication device may transmit the first and second sub-blocks as an encoded information block to the second wireless communication device.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Bilal Sadiq, Jamie Menjay Lin, Yang Yang, Gabi Sarkis, Tao Luo
  • Patent number: 10866857
    Abstract: There is provided a method of obtaining one or more parity symbols (PS) of an encoding of information symbols (IS) according to a linear cyclic code, the method comprising: upon a permutation of information symbols (IS), generating data indicative of parity coefficients of a row of a generator matrix associated with the linear cyclic code, computing, for each given parity coefficient, a first data in accordance with, at least, the given parity coefficient and the first IS; updating, by the processing circuitry, for each given parity coefficient of the one or more parity coefficients, the first data, in accordance with, at least, the given parity coefficient and the respective IS; and upon meeting a parity completion criterion for a given parity coefficient, deriving a parity symbol from the respective first data, thereby obtaining the one or more parity symbols of the codeword of the linear cyclic code.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TSOFUN ALGORITHMS LTD.
    Inventors: Noam Presman, Eldad Meller, Alexander Smekhov, Nissim Halabi
  • Patent number: 10859628
    Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Apple Ine.
    Inventors: Bibo Li, Bo Yang, Vijay M. Bettada, Matthias Knoth, Toshinari Takayanagi
  • Patent number: 10852353
    Abstract: An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mudasir Shafat Kawoosa, Vishal Diwan
  • Patent number: 10838808
    Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes, Saket Jalan
  • Patent number: 10838660
    Abstract: A method includes receiving, by a computing entity of a dispersed storage network (DSN), a request from a requesting device of the DSN to perform an encoded data slice operation. The request includes an indication that the encoded data slice operation is a stage in a predefined DSN workflow. The method further includes sending, by the computing entity, a response to the requesting device that includes a DSN workflow tag, wherein the DSN workflow tag includes an identifier of the stage in the predefined DSN workflow. The method further includes enabling a performance optimization mode. The performance optimization mode includes one or more performance optimization procedures for one or more of: the stage and one or more future stages of the predefined DSN workflow. The method further includes executing the encoded data slice operation in accordance with the performance optimization mode.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David E. Reese, Ethan S. Wozniak