Abstract: A method of etching a semiconductor substrate (11) includes thinning (102) the semiconductor substrate (11), providing (103) a support layer (30) for the semiconductor substrate (11), providing (104) an etch mask (28) over the semiconductor substrate (11), and etching (105) the semiconductor substrate (11) using an etchant mixture of hydrofluoric acid, nitric acid, phosphoric acid, sulfuric acid, and a wetting agent at a temperature below ambient. The method is capable of using one etch step (105) and one etch mask (28) to form a plurality of trenches (12, 13) having the same width (15, 17) but different depths (16, 18) and different orientations. The method can be used to singulate different sizes and configurations of semiconductor dice from the semiconductor substrate (11).

Abstract: A metallization system (19) for a semiconductor component (20) includes depositing a dielectric layer (12) over a substrate (10), etching a via (14) in the dielectric layer (12), sputtering a metal layer (17) of aluminum, copper, and tungsten over the dielectric layer (12) and in the via (14), and sputtering a different metal layer (18) of aluminum and copper over the first metal layer (17) and in the via (14). The metallization system (19) reduces the reliability issues associated with electromigration and stress migration while enhancing the ability to fill vias with large aspect ratios.

Abstract: A gate oxide layer and a polysilicon layer are formed in sequence over the major surface of a semiconductor substrate. A photoresist layer is formed on the polysilicon layer and an opening is formed in the photoresist layer. Using the photoresist layer as a mask, boron is ion implanted through the polysilicon layer and the gate oxide layer into the semiconductor substrate. Phosphorus is next ion implanted into the polysilicon layer by using the photoresist layer as a mask. Different ion species are ion implanted into the semiconductor substrate and the polysilicon layer, respectively, by using the same photoresist layer, thus decreasing the number of photoetching steps in manufacture of semiconductor devices.

Abstract: A method for producing a semiconductor device having a semiconductor layer of SiC is disclosed. The method comprises the steps of applying an insulation layer on the semiconductor layer, implanting first impurity dopant into the semiconductor layer, and annealing this layer at at least about 1500.degree. C. so that the implanted first impurity dopant is activated, wherein the insulating layer comprises AlN as a major component and the insulating layer is applied before the annealing step and maintained on the semiconductor layer during the annealing step.

Abstract: A method for fabricating a semiconductor device of the invention, the method includes the steps of: providing an oxygen concentration in a region of a silicon film of 1.times.10.sup.18 cm.sup.3 or less; depositing a film including a metal on the silicon film; and reacting the silicon film with the film including a metal so as to form a metal silicide film in the region of the silicon film.

Abstract: A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.

Abstract: A semiconductor chip package is produced using a lead frame which has an island where a plurality of through holes are formed corresponding to the electrodes of the semiconductor chip, respectively. After an insulating film is formed on the island, the semiconductor chip is fixed to one side of the island through an adhesive layer while aligning the electrodes of the semiconductor chip with the through holes of the island portion, respectively. After sealing the semiconductor chip with sealing resin, solder balls are formed on the other side of the island portion, the solder balls are connected to the electrodes of the semiconductor chip through the through holes of the island portion, respectively.

Abstract: In a method of manufacturing non-volatile semi-conductor memory including a memory cell transistor and a peripheral transistor, a floating gate and a control gate of the memory cell transistor is formed on a semiconductor substrate and a gate electrode of the peripheral transistor is formed on the semiconductor substrate. The control gate and gate electrode are covered with first and second insulating layers, respectively. A conductive layer is deposited to cover the first and second insulating layers. The conductive layer is etched back until the first and second insulating layers are exposed. An erasing gate of the memory cell transistor is formed by leaving the conductive layer on the insulating layer. A first mask layer on the second insulating layer and a second mask layer on the erasing gate is formed. The conductive layer remaining in the regions outside the masks is removed.

Abstract: Disclosed is a method for the shallow junction having a low sheet resistance and an improved electric characteristics, using the medium temperature CVD oxide layer deposited on the source/drain regions into which impurity ions are implanted. The medium temperature CVD oxide layer, which has a compressive stress of 1.53.times.10.sup.9 dyne/cm.sup.2, causes the surface of the silicon substrate to be subject to tensile stress. By forming the medium temperature CVD oxide layer on the silicon substrate at a temperature of approximately 760.degree.-820.degree. C., the defects in the inside of the substrate move to the surface of the silicon substrate. As a result, the concentration of the defects in the inside of the silicon substrate decreases so that the small size extended defects are on the surface of the silicon substrate. These extended defects can be naturally removed from the surface of the silicon substrate by performing a follow-up process such as a metalization or an additional thermal treatment process.

Abstract: N- and P-channel transistor characteristics are independently optimized for CMOS semiconductor devices with design features of 0.25 microns and under. Removable second sidewall spacers are formed on the N-channel transistor gate electrode having first sidewall spacers thereon. Ion implantation is conducted to form N-type moderately/heavily doped implants followed by activation annealing. The second sidewall spacer is then removed from the P-channel transistor leaving first sidewall spacers thereon serving as an ion implantation mask for the P-type lightly doped implants. Subsequently, third sidewall spacers are formed on the P-channel gate electrode having first sidewall spacers thereon followed by ion implantation to form the P-type moderately or heavily doped implants, with subsequent activation annealing. Embodiments enable complete independent control of the channel lengths of the N- and P-channel transistors by varying the width of the first, second and third sidewall spacers.

Abstract: A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.

Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.

Abstract: This invention relates to a process and structure for performing a high temperature or other process on both sides of a thin slice of material or die prior to being placed onto a integrated circuit or multi-chip module. In a particular embodiment, a process and structure is given to provide for double sided interdiffusion for passivation of a Mercury Cadmium Telluride (MCT) film which is mounted to a read-out integrated circuit (ROIC) face side up in order to fabricate vertically integrated Focal Plane Arrays (FPAs) with reduced dark currents and improved performance. The process of the present invention also allows for the insertion of novel materials such as Double Layer Heterojunction (DLHJ), MBE, MOCVD, etc. in the vertical integrated approach to FPAs.

Abstract: A fabrication method for a semiconductor memory device with a non-uniformly doped channel(hereinafter, called NUDC) formed in a semiconductor substrate with a thin central portion that becomes gradually thicker toward the edges of the substrate. The method includes forming an impurity-bearing layer on a semiconductor substrate, selectively etching the impurity containing layer in a manner such that the portion of the impurity-bearing layer serving as a gate region is formed to be thin at a central portion thereof and gradually thickens as it nears the edges thereof; forming a first conductive impurity region by driving the impurity from the impurity containing layer into the semiconductor substrate, stripping the impurity containing layer, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive impurity region in the semiconductor substrate at the sides of the gate electrode.

Abstract: A contact hole burying method is provided including the steps of: coating an oxide layer on a substrate and removing the oxide layer except for a portion thereof to form a contact hole extending through the oxide layer in electrical contact with the oxide layer; sequentially forming a metal barrier layer and wet layer on the oxide layer and inside the contact hole to form an electrical connection to the substrate; forming a conductive metal layer on the wet layer; removing impurity ions and oxide material, which remain in the conductive metal layer which decrease mobility of metal atoms on a surface of said conductive layer due to absorption and oxidation, by a cleaning-etching process using a plasma; and reflowing the conductive metal layer at a relatively low temperature in a reactive furnace where the cleaning-etching process is performed to completely fill the contact hole.

Abstract: A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide in the vicinity of the gates to be formed place the two conductive layers in contact with each other before the gates are formed and allows for the underlying conductive layer (usually the substrate) to be exposed to the plasma as the overlying unmasked conductive layer (usually polysilicon) is etched away. Preferably, the layer to be etched is deposited to be in contact with the underlying layer at the openings. This technique is applicable to integrated capacitor structures and other susceptible structures with a dielectric layer between two conductors.

Abstract: An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a subsurface P+ region below the entire bottom of an N+ "source" region of the IGBT. This low resistivity region suppresses thyristor latch-up when contacted via a surface trench. Self-aligned techniques provide method and product improvements.

Abstract: A SAM avalanche photodiode formed with an epitaxially regrown guard ring and a planar P-N junction defined between a cap layer and a multiplication layer. The multiplication layer is part of a multi-layer semiconductor platform having a conductivity opposite to the conductivity type of the cap layer, including a light absorption layer, a substrate and an intermediate layer. A second embodiment of the present invention is disclosed including a SAM avalanche photodiode having a guard ring with a variable distribution of impurity dopant concentrations. In addition, a third embodiment of the present invention is disclosed in which a narrow band gap layer completely covers the cap layer and a non-alloy metal contact is formed to completely cover the narrow band gap layer, forming a mirror junction. In this embodiment, incident light is shined through the substrate and reflected from the mirror junction, enhancing the absorption efficiency.

Abstract: A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.

Abstract: A reinforcing ring surrounding a semiconductor element connected electrically to respective interconnecting portions through electrodes is provided as one body through suspending portions. A film circuit is produced by forming a ring in place of an outer lead for instance by applying a lead frame forming technique in which a laminate of three layers or more is used as a base, an inner lead is formed on one side and an outer lead is formed by a surface layer on another side. In this manner, in a film circuit composed of an insulating film and a plurality of interconnecting portions (leads) electrically connecting between electrodes and other electronic components of a semiconductor element on at least one principal plane of the insulating film, it is made possible to align a ring surrounding a semiconductor element with respect to the semiconductor element only by placing the film circuit on the semiconductor element, and in its turn to reduce assembly mandays of a semiconductor device.