Abstract: A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant specie is an ionic molecule that contains titanium and boron.

Abstract: The invention provides a non-volatile semiconductor storage apparatus wherein silicon pillars are formed by epitaxial growth thereby to suppress a dispersion in channel length and improve the quality of a gate oxide film. In production, epitaxial silicon pillars are formed by selective epitaxial growth on a p-type silicon substrate, and a gate oxide film is formed over the overall area. Polycrystalline silicon is deposited and etched back to form a first polycrystalline silicon film serving as floating gates. Ion implantation is performed to form drain regions at the tops of the epitaxial silicon pillars and form a source region on the surface of the silicon substrate. A layered insulation film is formed, and polycrystalline silicon is deposited and etched back to form a second polycrystalline silicon film which covers over the side faces of the floating gates and serves as control gates. Bit lines are formed on the drain regions.

Abstract: A method is described for forming a dynamic random access memory cell with an increased capacitance capacitor. Semiconductor devices including a capacitor node contact region are formed. A layer of silicon nitride and an insulating layer are deposited over the devices. A contact is opened through the insulating and silicon nitride layers to the capacitor node contact region. A first layer of polysilicon is deposited over the insulating layer and within the contact opening. A layer of silicon oxide is deposited over the first polysilicon layer. The silicon oxide layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a first distance. The first polysilicon layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a second distance smaller than the first distance. A second layer of polysilicon is deposited over the silicon oxide layer.

Abstract: In a method of manufacturing semiconductor chips for display, a semiconductor thin film is first formed on an insulating substrate, and then a series of processes including a heat-treatment process for the semiconductor thin film are carried out to form integrated thin film transistors on a sectioned area for one chip. Thereafter, pixel electrodes for one picture (frame) are formed within the sectioned area. During the series of processes, a laser pulse is irradiated onto the sectioned area by one shot to perform a heat treatment on the semiconductor thin film for one chip collectively and simultaneously (i.e., perform a batch heat treatment on the semiconductor thin film). Through the batch heat treatment, the crystallization of the semiconductor thin film is promoted. In addition, after the semiconductor thin film is doped with impurities, the activation of impurities doped in the semiconductor thin film can be performed by the batch heat treatment.

Abstract: A radiation-hard isoplanar cryo-CMOS process suitable for submicron device fabrication reduces channel length to submicron levels. A channel stop (52) is formed after a first polysilicon gate (50) is formed to reduce the space between a n-/n+ source/drain region (67, 68) and the channel-stop region (52). Double gate oxidation steps are performed to increase polyoxide thickness. A thermal oxide masking step is carried out to obtain a thin layer of gate oxide under a second polysilicon gate (60A) for CMOS devices. The process includes two different second polysilicon masking steps to provide dimension control of second polysilicon gates (60A) and to remove bridging of the second polysilicon where the second polysilicon layer (58) is over the first polysilicon layer (48).

Abstract: Following with the formation of pad insulator layer and a stacked layer stacked, a gate insulator is formed within the defined gate insulator space. A lightly doped region is doped and the stacked layer and the pad insulator layer is removed. A semiconductor layer is formed and a gate space is defined over the gate insulator through a spacer structure. An anti punchthrough region is formed followed by the formation of a first insulator layer. A gate filling is then formed to fill within the gate space. A portion of the first insulator layer is then removed. A step of doping a plurality of junction ions is applied. A second insulator layer is formed and a thermal process is then proceeded. Finally a metalization process is employed on the semiconductor substrate.

Abstract: The present invention relates to a method for forming a TiNO metallic barrier layer acting as a diffusion barrier to intercept the diffusing of the Si atoms between metal layers, the method comprising the steps of: forming a TiN film through a sputtering equipment using Ar and N.sub.2 gas; implanting N.sub.2 O gas on the upper part of the TiN film; and annealing the resulting structure at N.sub.2 atmosphere for diffusing oxygen ions, thereby forming said resulting structure into uniform TiNO film.

Abstract: An IGFET with a gate electrode and a source contact in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, a source contact on the bottom surface, insulative spacers between the gate electrode, the source contact and the sidewalls, and a source and drain adjacent to the bottom surface.

Abstract: An apparatus and method for evenly applying an atomized adhesive for bonding a die to a leadframe is disclosed. In one embodiment, the apparatus includes a hood in communication with an air supply and a vacuum plenum that encompass a semiconductor device component located in a target area during adhesive application so that the adhesive is selectively applied to specific portions of the leadframe or other semiconductor device component and adhesive is not allowed outside the system. A mask or stencil may be employed for further prevention of adhesive application to undesired areas. An air purge may be employed to direct the adhesive mist toward the component to be coated. In another embodiment, a fine adhesive spray is directed against the surface of the workpiece to be coated, selected areas being masked to prevent coating. Wafers may be coated as well as leadframes.

Abstract: Method for testing bare semiconductor die which includes providing a test substrate with a die receiving surface and bond pads with conductive traces which extend away from the surface and are connected to leads that may be contacted with test probes. A vacuum source is applied to an aperture in the die receiving surface. Atmospheric pressure holds the die in place during the connection of thin wires. After connection, the die is held in place during testing by the thin wires.

Abstract: The present invention discloses a method of forming an oxide layer on a layer of gallium arsenide, including the steps of depositing a layer of aluminum arsenide on the layer of gallium arsenide, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide during the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a GaAs field effect transistor by forming an oxide layer on GaAs and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the gallium arsenide field effect transistor.

Abstract: A method of etching a III-V compound semiconductor uses an etching gas including the group V element of the III-V compound semiconductor substrate layer while keeping the III-V compound semiconductor layer at a temperature higher than the crystal growth temperature of the III-V compound semiconductor. Etching using this method provides a higher degree of controllability than wet etching. In addition, because no etching solution is employed, the etching method can be employed in a crystal growth apparatus. Further, because an element of the III-V compound semiconductor layer is employed in the etching gas, incorporation of residual impurities can be prevented, keeping the etched surface clean.

Abstract: The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the bottom. A conductive material is then formed in the contact opening in electrical contact with a lower conductive layer. The conductive material forms a plug having an enlarged head, such as a nail head or a flat heat screw shape. The enlarged head protects the silicon and a barrier layer, if present, within the contact from being etched by any subsequent anisotropic etches. Thus, when an electrical interconnection layer such as aluminum is formed overlying the contact plug, the plug acts as an etch stop to prevent etching of a barrier layer of the barrier layer within the contact opening.

Abstract: A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: During the etching of a silicon-containing material using a halogen-containing etch gas, a silicon-hydride gas is added to the etch gas to provide increased sidewall protection during the etch. Suitably up to about 50 percent by volume of a silicon-containing gas such as silane is added to improve anisotropy of the etch and to prevent notching at the silicon-substrate interface.

Abstract: A semiconductor having at least one p-channel transistor (10) with shallow p-type doped source/drain regions (16 and 18) which contain boron implanted into the doped regions (16 and 18) in the form of a compound which consists of boron and an element (or elements) selected from the group which consists of element of substrate (21) and elements which forms a solid solution with the substrate (21). In particular, in the case of silicon substrate, the compound may comprise BSi2, B2Si, B4Si and B6Si. The use of such compounds enables the highly reliable contacts to be formed on the p-doped regions.

Abstract: A method for production of high specific surface area silica gel by hydrolysis of silicon tetrahalide, wherein a solution of silicon tetrahalide in a non-reactive solvent such as alcohol is mixed with water to produce silica gel having a high surface area and narrow pore diameter distribution especially suited for use as normal phase packing material in high performance chromatography columns. The water contains fluoride ions if the halide is chloride. Reverse phase packing material can be prepared by reacting the normal phase silica gel with organochlorosilanes to prepare bonded reverse phase material for use in high performance liquid chromotagraphy systems.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: In order to fabricate a high performance thin film semiconductor device using a low temperature process in which it is possible to use low price glass substrates, a thin film semiconductor device has been fabricated by forming a silicon film at less than 450.degree. C., and, after crystallization, keeping the maximum processing temperature at or below 350.degree. C.In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.