Patents Examined by John Ruggles
  • Patent number: 8034543
    Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees from the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: October 11, 2011
    Assignee: GLOBAL FOUNDRIES Singapore Pte. Ltd.
    Inventors: Gek Soon Chua, Sia Kim Tan, Qunying Lin, Cho Jui Tay, Chenggen Quan
  • Patent number: 8029949
    Abstract: Disclosed is a photomask for forming a contact hole arranged on a wafer in a zigzag form along a transverse direction, including: a light transmitting substrate; a main pattern disposed on the light transmitting substrate with a zigzag form as an upper main pattern disposed in a relatively upper portion and a lower main pattern disposed in a relatively lower portion are arranged alternately along a transverse direction; a first lower auxiliary pattern extending in a vertical direction and disposed adjacently to a lower portion of the upper main pattern; a first upper auxiliary pattern extending in a vertical direction and disposed adjacently to an upper portion of the lower main pattern; a second lower auxiliary pattern extending in the transverse direction and connecting the first lower auxiliary patterns with each other; and a second upper auxiliary pattern extending in the transverse direction and connecting the first upper auxiliary patterns with each other.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun Jo Yang, Dong Sook Chang
  • Patent number: 8026023
    Abstract: A lithographic pellicle is provided that includes a pellicle frame, a pellicle film stretched over one end face of the pellicle frame via a pellicle film adhesive, and an exposure master plate adhesive provided on the other end face, wherein corners formed between a pellicle film adhesion face and exposure master plate adhesion face of the pellicle frame and inside and outside faces of the frame are subjected to C chamfering, and the chamfer dimension on the exposure master plate adhesion face is greater than C0.35 (mm) but no greater than C0.55 (mm).
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: September 27, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Yuichi Hamada
  • Patent number: 8017287
    Abstract: A development method according to an embodiment includes exposing a photosensitive film formed on a substrate at a predetermined exposure amount, carrying out a first development process that develops the exposed photosensitive film at a predetermined first development condition so as to leave the photosensitive film, obtaining a sensitivity information of an unexposed photosensitive film on the substrate from a film thickness reduction of the photosensitive film developed by the first development process and the predetermined exposure amount, predicting pattern dimensions of multiple types of patterns to be formed when a second development process is carried out following the first development process from the sensitivity information, and determining a first acceptable range of a development condition in the second development process, determining a second acceptable range of the development condition in the second development process from the first acceptable range and a variation amount of pattern dimensio
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Sakurai, Masatoshi Terayama
  • Patent number: 8007962
    Abstract: A photomask includes a base, a plurality of chip pattern regions over which a light shielding pattern of a metal material is defined, the plurality of chip pattern regions being defined on the base, scribe regions defined between the chip pattern regions, the scribe regions being defined by using the light shielding pattern, and slits in which the light shielding pattern is not defined, the slits being defined so as to surround the chip pattern regions.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 30, 2011
    Assignee: Sony Corporation
    Inventors: Keisuke Hatano, Takeshi Matsunuma, Shinji Miyazawa
  • Patent number: 8003302
    Abstract: Disclosed herein is a method for fabricating a pattern using a photomask that includes forming a first light shielding layer pattern over a substrate; forming a first resist layer pattern aligned to the first light shielding layer pattern over the first light shielding layer pattern; forming a phase shift region by selectively etching a portion of the substrate exposed by the first light shielding layer pattern; forming a second resist layer pattern by reducing the line width of the first resist layer pattern; forming a second light shielding layer pattern, having a reduced line width, by etching an exposed portion of the first light shielding layer pattern, and exposing a portion of the substrate adjacent the groove to form a rim region; removing the second resist layer pattern to form a photomask; and transferring a second pattern onto a wafer by performing an exposure process using the photomask.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 23, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Ho Ryu
  • Patent number: 7984392
    Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: July 19, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Kuo-Kuei Fu
  • Patent number: 7981576
    Abstract: A method of generating complementary masks for use in a dark field double dipole imaging process. The method includes the steps of identifying a target pattern having a plurality of features, including horizontal and vertical features; generating a horizontal mask based on the target pattern, where the horizontal mask includes low contrast vertical features. The generation of the horizontal mask includes the steps of optimizing the bias of the low contrast vertical features contained in the horizontal mask; and applying assist features to the horizontal mask. The method further includes generating a vertical mask based on the target pattern, where the vertical mask contains low contrast horizontal features. The generation of the vertical mask includes the steps of optimizing the bias of low contrast horizontal features contained in the vertical mask; and applying assist features to the vertical mask.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 19, 2011
    Assignee: ASML Masktools B.V.
    Inventors: Duan-Fu Stephen Hsu, Sangbong Park, Douglas Van Den Broeke, Jang Fung Chen
  • Patent number: 7972750
    Abstract: The mask blank is patterned to form a corresponding mask having a light shielding film pattern with enhanced resolution. A mask blank (10) on which a chemically amplified resist film (20) is formed, the mask blank (10) comprising a substrate (12), a light shielding film (13) provided on the substrate (12), and a resist underlying film (18) provided on the light shielding film (13), for suppressing the deactivation of the chemically amplified resist film (20). When the light shielding film (13) is etched using the patterned chemically amplified resist film (20) as a mask, the etching rate of the deactivation preventive film (18) is higher than the etching rate of the chemically amplified resist film (20).
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 5, 2011
    Assignee: Hoya Corporation
    Inventor: Masahiro Hashimoto
  • Patent number: 7968257
    Abstract: A halftone mask includes a shielding pattern partially formed on a transparent substrate; a first halftone transmission pattern partially formed on the transparent substrate; and a second halftone transmission pattern formed on the first halftone transmission layer. On this halftone mask, a width of the second halftone transmission pattern is narrower than a width of the first halftone transmission pattern.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: June 28, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Ji No Lee
  • Patent number: 7968252
    Abstract: The present invention is directed to reduce pellicle frame distortions due to the tension of a pellicle film and caused during handling, thereby providing an excellent pellicle frame capable of reducing the distortion of a photomask due to a pellicle affixation. In the pellicle frame of the present invention, the frame consists of a plurality of layers of which at least one layer has a different elastic modulus. It is preferable to: make the pellicle frame compositely of a layer having an elastic modulus of 10 GPa or smaller and of a layer having an elastic modulus of 50 GPa or greater; join these layers of the pellicle frame in a direction perpendicular to the pellicle film face; laminate such that layers having a large elastic modulus form the outermost layer; or reverse this lamination structure.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 28, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Toru Shirasaki
  • Patent number: 7968254
    Abstract: A photomask reticle for use in projection exposure to form a resist pattern on a workable film formed over a semiconductor substrate, includes a first area in which a light shield is formed, a second area formed around said first area, a third area formed around said second area; and a fourth area formed around said third area, the areas being formed over a substrate, a relationship between transmissivities of said areas being second area transmissivity>fourth area transmissivity>third area transmissivity>first area transmissivity.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: June 28, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Masayoshi Saito
  • Patent number: 7964326
    Abstract: A divided exposure method for a photolithography process is disclosed, which uses a mask. The mask for an exposer having a left and right light intensity deviation includes a substrate; a first pattern in a middle of the substrate; and second and third patterns on left and right sides of the first pattern, respectively, wherein the first and second patterns compensate for the left and right light intensity deviation of the exposer.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: June 21, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Su Woong Lee, Sang Yoon Paik
  • Patent number: 7955763
    Abstract: A method of manufacturing a mask blank glass substrate or mask blank that includes a mark forming step, and a mask blank glass substrate or mask blank that includes a mark. The mark is a pit formed by irradiating laser light onto a mirror-like surface in an area, having no influence on transfer, on a surface of the mask blank glass substrate. The pit is used as a marker for individually identifying or managing the mask blank glass substrate. The marker may be correlated with information including at least one of substrate information about the mask blank glass substrate, thin film information about the mask pattern thin film, and resist film information about the resist film. A mask blank glass substrate with marker correlated to at least one of the resist film information and thin film information may be used to manufacture a new mask blank.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: June 7, 2011
    Assignee: Hoya Corporation
    Inventors: Akinori Kurikawa, Hisashi Kasahara, Yasushi Okubo
  • Patent number: 7927766
    Abstract: A method includes determining defect types and defect locations on a mask blank and storing the defect types and the defect locations. The method further includes generating at least one alignment mark on the mask blank and selecting a mask pattern for the mask blank based on the defect types and the defect locations. Additionally, the method includes determining a positioning of the mask pattern on the mask blank, aligning a mask pattern generator with the mask blank in accordance with the positioning using the at least one alignment mark and forming the mask pattern on the mask blank using the mask pattern generator.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Monica J. Barrett, Kevin W. Collins, Daniel B. Sullivan
  • Patent number: 7914951
    Abstract: A method of correcting a pattern critical dimension of a photomask includes forming a phase shift layer and a light blocking pattern on a substrate, measuring a critical dimension (CD) of the light blocking pattern, and forming a negative resist pattern that has a relatively smaller CD than the CD of the light blocking pattern on the light blocking pattern, and correcting the CD of the light blocking pattern by etching the light blocking pattern exposed by the negative resist pattern. The method may further include forming a phase shift pattern by etching the phase shift layer exposed by the corrected light blocking pattern and the negative resist pattern as an etch mask, and removing the negative resist pattern and the corrected light blocking pattern.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: March 29, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Cheon Shin
  • Patent number: 7912275
    Abstract: A method of evaluating a photo mask, includes measuring each dimension of a plurality of pattern portions of a mask pattern formed on a photo mask, obtaining an inter-pattern distance between the pattern portion and a pattern different from the pattern portion with respect to each of the pattern portions, obtaining a dimensional difference between the measured dimension of the pattern portion and a target dimension of the pattern portion with respect to each of the pattern portions, grouping the dimensional difference obtained for each pattern portion into a plurality of groups in accordance with the inter-pattern distance obtained for each pattern portion, obtaining an evaluation value based on the dimensional difference in each group with respect to each of the groups, and evaluating the photo mask based on the evaluation value.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Yamamoto, Masamitsu Itoh, Osamu Ikenaga, Shoji Mimotogi, Hideki Kanai, Yukiyasu Arisawa
  • Patent number: 7906256
    Abstract: A used large-size photomask substrate having a patterned light-shielding film is recycled by (i) removing the light-shielding film from the used substrate to provide a photomask-forming glass substrate stock, (ii) resurfacing the glass substrate stock by sand blasting, (iii) repolishing the resurfaced glass substrate stock to yield a regenerated glass substrate stock, (iv) applying a light-shielding film onto the regenerated glass substrate stock to yield a regenerated photomask-forming blank, and (v) processing the light-shielding film of the blank into a pattern corresponding to a desired exposure of a mother glass, yielding a regenerated photomask substrate.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: March 15, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shuhei Ueda, Yukio Shibano
  • Patent number: 7901844
    Abstract: A method for fabricating a photomask includes forming a light blocking layer, a hard mask layer, and a resist layer on a transparent substrate, forming a resist pattern to selectively expose the hard mask layer by removing the resist layer selectively, forming a hard mask pattern by etching the exposed hard mask layer using the resist pattern as an etch mask, exposing the hard mask pattern by removing the resist pattern; measuring a critical dimension of the exposed hard mask pattern, correcting the measured critical dimension of the hard mask pattern to correspond to a critical dimension of a target pattern, forming a light blocking pattern by etching the exposed light blocking layer using the corrected hard mask pattern as an etch mask, and removing the hard mask pattern.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Joong Ha
  • Patent number: 7883823
    Abstract: A method of manufacturing a semiconductor device that includes: a first exposing step using a photomask in a first area of a semiconductor substrate; and a second exposing step using the photomask in a second area adjacent to the first area of the semiconductor substrate. The photomask includes a first transmitting pattern having a ring shape that is missing a part, and a supplemental second transmitting pattern having a shape corresponding to the missing part of the first transmitting pattern, so that a closed loop pattern is exposed by the first exposing step and the second exposing step on the semiconductor substrate.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyuki Ishiwata