Patents Examined by John S. Heyman
  • Patent number: 7508466
    Abstract: An LCD display includes a planar array of transmissive liquid crystal display (LCD) devices, and at least one laser diode device spaced apart from the planar array of LCD devices and configured to illuminate at least a subset of the LCD devices of the planar array of LCD devices such that, in operation, the laser diode device provides backlighting for the subset of LCD devices of the planar array of LCD devices.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: March 24, 2009
    Assignee: Cree, Inc.
    Inventor: Edward Lloyd Hutchins
  • Patent number: 7486343
    Abstract: A thin film transistor array panel including a substrate; a gate line formed on the substrate; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the semiconductor layer; a drain electrode separated from the data line and formed on the semiconductor layer; a coupling electrode connected to the drain electrode; a first subpixel electrode connected to the drain electrode; and a second subpixel electrode separated from the first subpixel electrode and overlapping the coupling electrode.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Kyu Hong, Joo-Han Kim, Jae-Jin Lyu, Sung-Hwan Hong, Won-Jae Lee
  • Patent number: 7483090
    Abstract: The invention provides a liquid crystal display including a thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a gate line formed on the substrate; a data line crossing the gate line; a thin film transistor connected to the gate and data lines; and a pixel electrode including first and second subpixel portions electrically connected to the thin film transistor, and a third subpixel portion capacitively coupled to at least one of the first and the second subpixel portions. Such an arrangement of a TFT permits a distribution of the tilt directions of liquid crystal molecules in the same pixel to improve lateral viewing of the liquid crystal display.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ju Shin, Chang-Hun Lee, Cheol-Woo Park, Chong-Chul Chai
  • Patent number: 7477339
    Abstract: A liquid crystal display device includes a liquid crystal panel including a first substrate, a second substrate, and a liquid crystal layer disposed therebetween; and a backlight assembly including a plurality of lamps disposed in a first direction to provide light to the liquid crystal panel, and a plurality of lamp guides to fix the plurality of lamps, at least one of the lamp guides having a guide plate and a plurality of lamp fixing parts, wherein a first one of the lamp fixing parts is disposed on the guide plate at a lamp fixing part axis in a second direction perpendicular to the first direction, and wherein a second one of the lamp fixing parts is disposed on the guide plate space apart from the lamp fixing part axis.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 13, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung Sub Kim, Seok Hwan Oh
  • Patent number: 7450211
    Abstract: A liquid crystal display device is disclosed that is capable of suppressing disorder of alignment of liquid crystal molecules caused by a spacer arranged between two TFT substrates. In liquid crystal display device, the spacer arranged between the two TFT substrates is capable of aligning liquid crystal molecules near the spacer along a specified direction.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: November 11, 2008
    Assignees: Fujitsu Limited, Au Optronics Corporation
    Inventors: Arihiro Takeda, Takahiro Sasaki, Manabu Sawasaki
  • Patent number: 5638418
    Abstract: A temperature detector comprises temperature sensing circuitry calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a value that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry. Alternate embodiments of the temperature detector comprise temperature sensing circuitry, calibration circuitry, and resolution enhancement circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: June 10, 1997
    Assignee: Dallas Semiconductor Corporation
    Inventors: James M. Douglass, Gary V. Zanders, Donald R. Dias, Robert D. Lee
  • Patent number: 5585747
    Abstract: A differential sense amplifier is provided wherein a first amplifier stage is biased to minimize current consumption of all stages of the amplifier and to provide outputs of the first stage that are high enough in voltage to allow proper operation of a second stage of the amplifier, yet low enough in voltage to allow a current mirror to be integrated into the second stage of the amplifier. The integration of the third stage current mirror into the second stage amplifier reduces capacitive loading on the outputs of the second stage increasing speed while eliminating the extra power normally associated with a separate current mirror. This combination results in a very fast, yet very low power amplifier.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: December 17, 1996
    Inventor: Robert J. Proebsting
  • Patent number: 5572561
    Abstract: A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: November 5, 1996
    Assignee: Fujitsu Limited
    Inventors: Kunihiro Usami, Miki Kubota
  • Patent number: 5559844
    Abstract: A binary counter or binary-coded-arithmetic counter uses local look-ahead to speed up ripple carry propagation. A succession of counter stages therein can be identified by respective consecutive ordinal numbers assigned in accordance with the order of carry propagation. Each counter stage receives a respective carry input and supplies a respective output signal, and each counter stage identified by even number supplies a respective complemented output signal. Each counter stage identified by odd number has a respective carry generation circuit for supplying a respective carry output signal which includes a NAND gate responsive to carry input to that counter stage and responsive to output signal from that counter stage, carry input for the next counter stage being supplied in response to the NAND gate response.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: September 24, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Si-Yeol Lee
  • Patent number: 5548234
    Abstract: A two-step solid state optical switch system includes an electro-optical material positioned between a first electrode and a grounded second electrode. A voltage source is electrically connectable to the first electrode by an ON switch. When the ON switch is closed, a plurality of field effect transistors establish electrical contact between the voltage source and the first electrode to charge the first electrode and change the optical characteristics of the electro-optical material. An OFF switch, which is also electrically connectable to the first electrode, includes a plurality of field effect transistors, which establish electrical contact between ground and the first electrode when the OFF switch is closed. With the closing of the OFF switch, any voltage on the first electrode is removed to restore the optical characteristics of the electro-optical material.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: August 20, 1996
    Assignee: Intelligent Surgical Lasers, Inc.
    Inventors: Laszlo Turi, Richard Ujazdowski, Tibor Juhasz
  • Patent number: 5539795
    Abstract: A sector pulse generating apparatus for multiple zone recording includes only first and second counters. The first counter counts reference clock pulses and outputs a present position signal. The second counter is incremented in response to a increment signal and outputs a next sector number signal. A first register stores the sector length of a zone in which a head is located. A multiplier outputs a next sector position signal representative of a multiplication of the next sector number and the sector length. A first comparator compares the magnitude of the present position and the next sector position. When the present position and the next sector position match, a sector pulse generating device generates a sector pulse and a first increment device outputs the increment signal.
    Type: Grant
    Filed: July 3, 1995
    Date of Patent: July 23, 1996
    Assignee: NEC Corporation
    Inventor: Yasuhiro Takase
  • Patent number: 5537067
    Abstract: A signal driver circuit (10) is provided that comprises a first inverter comprising a P-FET (14), an N-FET (16) and a resistor (18). A second inverter comprises a P-FET (20) and an N-FET (22). Resistor (18) and capacitors (24) and (26) limit the transition times of the output driving signal to control electromagnetic radiation caused by rapid transition times in the output signal. Circuit (10) is independent of the amount of capacitive load (28) driven by the circuit.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: July 16, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Fernando D. Carvajal, David D. Briggs
  • Patent number: 5534844
    Abstract: A static-type comparator, which compares the magnitude of a first binary number with a second binary number and determines if the first binary number is equal to, greater than, or less than the second binary number, is described. The comparator comprises a carry chain of comparison cells. Each comparison cell in the carry chain compares the magnitude of a different bit position of the first number with a corresponding bit position in the second number. The comparison cells input a first voltage signal, representing a binary value of a bit position of the first number, and a second voltage signal, representing a binary value of a corresponding bit position of the second number. A voltage signal from a voltage source Vcc is input into the carry chain and propagates through the chain until a comparison cell detects that there is a difference in magnitudes for a particular bit position.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: July 9, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David Norris
  • Patent number: 5533079
    Abstract: Inventory monitoring apparatus capable of real-time counting of objects added to or subtracted from a location whose inventory is to be monitored. The apparatus includes structure for supporting a plurality of objects and at least one lever adapted to be contacted and displaced by movement of the objects to and from the supporting structure. Movement of the lever in one direction triggers a switch which generates a signal indicating that an object is being added to the support structure. Similarly, opposite movement of the lever triggers another switch which generates a signal indicating that an object is being removed from the support structure. A microprocessor receives and counts the signals generated by the switches to provide a real-time total of the quantity and, if desired, the locations of objects borne by the supporting structure.
    Type: Grant
    Filed: January 25, 1994
    Date of Patent: July 2, 1996
    Assignee: MedSelect Systems, Inc.
    Inventors: Eric R. Colburn, Max A. Fedor, Robert G. Gillio, Daniel W. Neu
  • Patent number: 5532623
    Abstract: A sense amplifier includes: a pull-down device which contains a reference cell which is structurally identical to the PLD cells being sensed; and a pull-up device connected to form a current mirror which causes a saturation current of the pull-up device to be zero or greater than the current through the sensed cell. The pull-down device has a saturation current which tracks the current through the sensed cell. When current flows through the sensed cell, saturation current through the pull-up device exceeds the saturation current through the pull-down device, and an output node is pulled up. When no current flows through the sensed cell, no current flow through the pull-up device, and the pull-down device pulls the output node down. As a result, the sense amplifier exhibits a variable trip point which tracks variations cause by changes in device fabrication process, temperature, and power supply voltage.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: July 2, 1996
    Assignee: WaferScale Integration, Inc.
    Inventors: Manik Advani, Cuong Trinh
  • Patent number: 5532626
    Abstract: An off-line controller circuit having a line voltage detector and a switched current bootstrap circuit. The controller receives current from the line and provides a drive signal for controlling the switch(es) of an off-line converter. The line voltage detector establishes a voltage proportional to the line voltage in response to a portion of the received line current. The proportional voltage is compared to a reference voltage to provide a control signal for inhibiting the drive signal when the proportional voltage is less than the reference voltage, indicating that the line voltage is less than a predetermined level. The switched current bootstrap circuit limits a bootstrap current provided to the controller supply voltage from the converter output in accordance with current shunted to ground by a supply voltage clamp.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: July 2, 1996
    Assignee: Unitrode Corporation
    Inventor: Joseph M. Khayat
  • Patent number: 5530730
    Abstract: A medal counting apparatus installed in a game parlor for counting medals which a game player has won, is disclosed. The medal counting apparatus comprises a counter for counting the medals, a medal supplying mechanism for receiving the medals to be dumped and for supplying them sequentially to the counter, a dump restraining unit for restraining the medals from being dumped into the medal supplying mechanism and a control unit for controlling operations of the medal supplying mechanism and the dump restraining unit. The medal supply control means puts the medal supplying mechanism into a stopped state when the dump restraining unit restrains the medals from being dumped and into an operation state when the dump restraining unit permits dumping of the medals. The control unit also instructs the dump restraining unit to close the receiving hopper when a medal dump restraining signal is input from the outside or the counter has not been used for a certain period of time.
    Type: Grant
    Filed: December 13, 1994
    Date of Patent: June 25, 1996
    Assignee: Kabushiki Kaisha Ace Denken
    Inventors: Takatoshi Takemoto, Koichi Tsubota, Masao Minagawa, Moriyuki Aoyama
  • Patent number: 5528193
    Abstract: A simple operational amplifier is coupled to a pair of resistors such that a positive reference voltage is reliably converted to a negative voltage. The op amp includes a differential pair of pnp transistors to which is connected a npn transistor connected as an emitter follower. The op amp is constructed and operated such that the bases of the pnp transistors and the collector of the npn transistor never fall below ground voltage.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: June 18, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Michael X. Maida
  • Patent number: 5526393
    Abstract: A synchronous counter comprises one D flip-flop circuit for performing divide-by-2 frequency division of a clock signal CK, JK flip-flop circuits for, when input signals have HIGH levels (logical value 1), inverting the levels of the output signals in synchronization with the clock signal CK, logic circuits for inputting control signals to the JK flip-flop circuits, lower-stage signal assembling circuits for grouping the output signals from the JK flip-flop circuits into two-signal-unit groups to produce logical product signals of the signals in these two,signal-unit groups, and upper-stage signal assembling circuits for further handling the output signals from the lower-stage signal assembling circuits, thereby firstly simultaneously satisfying an increase in speed of the counting operation as well as simplification of the wiring pattern and reduction in the circuit area and secondly realizing further increase in the counting operation.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: June 11, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Mitsuaki Kondo, Takamoto Watanabe
  • Patent number: 5526392
    Abstract: A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2.sup.M times the number of clock signals that have been input to the counter. The first M stages of the counter are selectively held so that clock signals by-pass (or pass through) the first M stages without change. The M+1 stage receives each clock signal and is thereby caused to indicate that 2.sup.M clock signals have been received, when only one clock signal has, in fact, been received. The output of each stage is provided to a decoder array that provides the scaled count signal. The method and circuit find application in systems in which normal unscaled operation of the binary counter may be selectively replaced with high speed operation, such as during tests or during special operating modes. The circuit and method obviate the need for a separate high speed clock, or for adaptive circuitry in the decoder array.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: June 11, 1996
    Assignee: Harris Corporation
    Inventors: Paul K. Sferrazza, Joseph W. Harmon