Abstract: A method and apparatus for counting irregularly-shaped articles. A pair of light sources are provided at a sensing plane through which articles to be counted are adapted to pass. Each of the light sources emits a light beam that is at an angle to the other light beam, such as an angle of about 90.degree.. Corresponding solar cells are positioned opposite the respective light sources to receive the light signals as the articles pass through the sensing plane. The light sources are alternately operated and the outputs from the respective light detectors are used to calculate an equivalent volume for the article for comparison with a predetermined article volume range to decide whether to count the article. The method and apparatus permit accurate counts of irregularly shaped articles and are substantially independent of the orientation of the article at the sensing plane.

Abstract: A differential circuit is provided that generates a differential output voltage .DELTA.V that does not vary when the power supply voltage changes and/or when the field effect transistor conductance changes. The bias circuit connected to the differential amplifier stabilizes the output voltage swing .DELTA.V to be insensitive to change in supply voltage and/or transconductance. A feedback loop is provided to drive the voltage to a predetermined voltage dependent upon the threshold voltage of the transistors used (e.g., the threshold voltage of a PMOS transistor). The voltage stabilizes the current source of the differential amplifier via a current mirror coupled to the feedback loop. Therefore, the resultant differential output voltage .DELTA.V is equal to the transistor threshold voltage. As the transistor threshold voltage is independent of the power supply voltage and device transconductance, the differential amplifier output .DELTA.

Abstract: A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.

Abstract: A Gray code counter is provided having identical modular circuits with each odular circuit providing a Gray code count sequence having a predetermined number of bits and an enable signal to enable a successive modular circuit of the Gray code counter. Each modular circuit of the Gray code counter enables a successive modular circuit only during certain predetermined counts of the Gray code count sequence. The number of modules required to implement the counter is determined by the number of binary bits per module and the total number of binary bits provided by the counter. The Gray code counter can operate either in an up mode count or a down mode count in accordance with the Gray code count sequence.

Abstract: The invention relates to a multi-stage digital logic circuit in which, for example, it is possible to assign an output word (C0, . . . , C3) a minimum of two input words (A0, . . . , A3; B0, . . . , B3), and in which it is possible to form output bits (for example C3) having a high place value before output bits (for example C2, C1 or C0) having a lower place value.

Abstract: The hand held decimal timer circuit comprises: a power supply having a positive voltage output and a ground or common output; a counter circuit coupled to the power supply; a frequency divider circuit coupled to the counter circuit and to the power supply; a clock circuit including an oscillator coupled to the frequency divider circuit; a display circuit coupled to the counter circuit; a switch circuit coupled to the counter circuit; and, the frequency divider circuit including: (a) a first input for receiving a clock signal from the clock circuit, (b) a second input and a third input for receiving, respectively, a positive voltage reference and a ground voltage reference from the power supply, (c) a 12 bit binary counter which counts the clock cycles from the clock circuit and outputs, on a plurality of output pins, a number of clock cycles in binary form, (d) a pair of NAND gates each having at least three inputs and an output, the inputs being coupled to at least some of the plurality of output pins for re

Abstract: Apparatus for counting and selectively voiding tickets. An input bin is provided wherein a stack of tickets are initially queued. Using a conveyor, each ticket is advanced from the input bin past a sensing device. The sensing device detects the presence of each ticket and produces a signal indicative of the passage of each ticket past the sensing device. This signal is conveyed to an electronic counting device that maintains a cumulative total count of the tickets. The apparatus may be set to continuously count any tickets placed in the input bin or set to stop after counting a predetermined number of tickets. The apparatus also includes a punch that is selectively controlled to enable the optional voiding of each ticket as it is counted.

Abstract: A frequency stabilizing circuit for a .pi./4 QPSK (Quadrature Phase Shift Keying) signal receiver has a voltage controlled oscillator (VCO) for outputting an oscillation signal whose frequency changes in response to a control voltage applied to the VCO. A mixer changes the frequency of an input .pi./4 shift QPSK signal. A counter measures the frequency of the .pi./4 shift QPSK signal from the mixer. A timing generator generates, on the basis of the oscillation signal from the VCO, a timing indicative of an interval during which the counter is to measure the frequency. A set data generator generates a frequency signal having a predetermined set frequency. A comparator compares the frequency measured by the counter and the set frequency of the set data generator to thereby output the resulting frequency deviation. A voltage data generator changes voltage data in association with the frequency deviation. A digital-to-analog converter transforms the voltage data to the control voltage.

Abstract: The counting station has a transporting section (2b), on which the banderoled packs of notes (P) are moved at certain intervals uniformally past the rotating counting disk (1a, 1a') of a note-counting device (1, 1') fixedly installed on this transporting section. Downstream of the transporting section (2b) there is a diverter (9) with two further transporting sections (2c, 2d), of which one receives packs of notes having the correct number of notes of value and the other receives packs of notes having the incorrect number of notes of value.

Abstract: A counter system having associated counter error detection circuitry that utilizes the current parity, the previous parity, and a predicted parity for evaluating counter operation is described. In successive count cycles, a predicted parity is utilized, during the next subsequent count cycle is stored in flip-flop as the current parity, and in the next subsequent count cycle is stored a second flip-flop as a previous parity. Circuit are described for performing parity check and parity prediction functions. The previous parity, current parity and predicted parity will not be alike for any binary counter that operates properly. Circuity is described that holds and compares the parity of the Count, the current parity, and the previous parity, during each counter advance cycle and to provide an error signal when the counter is detected to be stuck.

Abstract: A gate drive circuit for a power switching device having first and second power terminals and a gate terminal comprises an H-bridge rectifier having first, second, third, and fourth rectifiers, the anodes of the first and second rectifiers being mutually coupled at a midpoint to the cathodes of the third and fourth rectifiers. This midpoint is coupled to the gate terminal of the power switching device. A continuous alternating waveform generator is coupled to output selection control logic which selectively applies the waveform to either a first transformer, whose secondary is coupled to the anodes of the third and fourth rectifiers of the H-bridge for transforming the waveform from a control signal reference system to a power signal reference system, or to a second transformer, whose secondary side is coupled to the cathodes of the first and second rectifiers of the H-bridge for transforming the waveform from the control signal reference system to the power signal reference system.

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remain high for most of the vertical interval.

Abstract: A frequency dividing circuit/delay circuit is provided to generate a plurality of system clock signals according to the combination of frequency division and the delay based on a fast-speed basic clock signal to determine according to the address signal from a central processing unit (CPU) what the operating cycle of the slave is to select a system clock of optimum frequency or duty ratio for that slave. As a result, it becomes possible to shorten the time required for executing one cycle and, hence, to improve the performance of the whole personal computer system.

Abstract: An asynchronous counter includes a plurality of flip-flops, cascade connected to one another, the plurality of flip-flops serially receiving successive pulse trains having varying numbers of pulses per pulse train. Switching circuitry, coupled to the plurality of flip-flops, inverts the state of each flip-flop between a first set of pulse trains and a second set of pulse trains (or first and second consecutive pulse trains) so that the counter computes a difference between the number of pulses in the first set of pulse trains and the number of pulses in the second set of pulse trains (or a difference between the number of pulses of the first pulse train and the number of the second pulse train). Initialization circuitry, coupled to the plurality of flip-flops, initializes all of the flip-flops at each predetermined even number of pulse trains.

Abstract: A reset mechanism of a counter for counting the number of times of image formation is mounted on an image forming apparatus. The image forming apparatus includes a unit constituting at least a part of an image forming section which is detachably mounted on a predetermined portion of the main body of the image forming apparatus, a driving mechanism for driving the unit, and a counter for counting the number of times of image formation for reporting the time for replacement of the unit. The reset mechanism has a reset switch provided for on the main body for resetting the counter, and an operating member which is provided for on the unit for operating the reset switch. If a unit which has not been used is mounted on the main body, the operating member which is previously set in the operating position resets the reset switch.

Abstract: A comparator is provided in the counter circuit to compare the counted value of clocks by a counter with the value of a register in which a target changing value of a comparison register which sets a value to be compared with the counted value of the counter is set. The value of the register is set in the comparison register when the counted value of the counter does not reach the set value of the register, whereas the value of the register is not set in the comparison register if the counted value does not reach the set value of the register, but the value of the comparison register is turned changeable at the desired timing while the counted value of the counter is being compared with the set value of the comparison register.

Abstract: An apparatus for counting occurrences of a particular input during a plurality of succeeding periods. The apparatus comprises an input terminal for receiving the input, a toggle signal generating circuit for generating a periodic toggle signal to mark the plurality of periods, and a plurality of n counter cell circuits for effecting the counting in n bits. Each counter cell circuit generates at least a respective bit output, a respective toggle output, and respective carry output. The counter cell circuits are arranged in hierarchical order from a least-significant counter cell circuit to a most-significant counter cell circuit.

Abstract: The device comprises a switched-mode power supply (1) equipped with an electronic switching member (T.sub.1), the closing of which controls the power supply to an inductor (L.sub.1) which discharges, when the member reopens, into a capacitor (C.sub.1) at the terminals of which the output voltage of the device appears, characterized in that it comprises (a) storage means for recording a sequence of image numbers of successive segments of the predetermined waveform, (b) a clocked digital counter (2) and (c) means (3) for successively loading this counter (2) with each of the numbers of this sequence considered as a bound of the count performed by the counter (2), the latter cyclically controlling the closing of the switching member (T.sub.1) for a predetermined time interval, each time the count performed reaches the limit thus fixed.

Abstract: The analyzer circuit includes a first oscillator producing an output signal having a first frequency depending on an inductance of an inductive position sensor having two oscillator coils positioned near a movable part; a switching device in the first oscillator for alternatingly connecting one of the two coils and simultaneously disconnecting the other according to a state of the switching device; a frequency divider for converting the output signal at the first frequency to another output signal at another frequency; a counter for counting a pulse signal under control of the other output signal of the frequency divider; a second oscillator connected to the counter and providing input pulses at a fixed frequency to the counter, which counts the input pulses under control of the other output signal of the frequency divider; a start synchronizing circuit for starting and synchronizing the divider and the counter; a flip-flop connected to the frequency divider and to the switching device to switch the state of

Abstract: A device and method for controlling the gain of a charge based signal is described. The described device and method may be used for both offset correction and for gain control. First and second charge holding gates are provided for receiving a charge packet representing a signal. A control gate partitions off at least a portion of the charge on the secondary charge holding gate. The charge not so partitioned off is then transferred onto the output line as the adjusted charge packet representing the adjusted signal, where the gain is now the ratio of areas of first charge holding gate to the sum of areas of both first and second charge holding gates. The offset of a signal can also be corrected by segregating the portion of charge representing the offset of an input signal onto the second charge holding gate.