Patents Examined by John S Ruggles
  • Patent number: 8956787
    Abstract: To provide an EUV mask blank provided with a low reflective layer, which has excellent properties as an EUV mask blank. A reflective mask blank for EUV lithography comprising a substrate, and a reflective layer for reflecting EUV light, an absorber layer for absorbing EUV light and a low reflective layer to an inspection light (wavelength: 190 to 260 nm) for a mask pattern, formed in this order on the substrate, wherein the low reflective layer has a stacked structure having a first layer containing at least 95 at % in total of silicon (Si) and nitrogen (N), and a second layer containing at least 95 at % in total of tantalum (Ta), oxygen (O) and nitrogen (N) or a second layer containing at least 95 at % in total of tantalum (Ta) and nitrogen (N), stacked in this order from the absorber layer side.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 17, 2015
    Assignee: Asahi Glass Company, Limited
    Inventors: Toshiyuki Uno, Kazuyuki Hayashi
  • Patent number: 8945802
    Abstract: A method for measuring flare information of a projection optical system includes arranging, on an object plane of the projection optical system, a sectoral pattern surrounded by a first side, a second side which is inclined at a predetermined angle with respect to the first side, and an inner diameter portion and an outer diameter portion which connect both ends of the first side and both ends of the second side; projecting an image of the sectoral pattern via the projection optical system; and determining the flare information based on a light amount of the image of the sectoral pattern and a light amount provided at a position away from the image. With the flare measuring method, it is possible to correctly measure the flare information in an arbitrary angle range of the sectoral pattern.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: February 3, 2015
    Assignee: Nikon Corporation
    Inventor: Masayuki Shiraishi
  • Patent number: 8927179
    Abstract: There are provided an EUV optical member, in which deterioration in the reflectivity due to oxidation of the Ru protective layer is prevented, a functional film-equipped substrate to be employed for production of the EUV optical member, and a process for producing the functional film-equipped substrate. A reflective layer-equipped substrate for EUV lithography comprising a substrate, and a reflective layer for reflecting EUV light and a protective layer for protecting the reflective layer, formed in this order on the substrate, wherein the reflective layer is a Mo/Si multilayer reflective film, the protective layer is a Ru layer or a Ru compound layer, and an intermediate layer containing from 0.5 to 20 at % of oxygen and from 80 to 99.5 at % of Si is formed between the reflective layer and the protective layer.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: January 6, 2015
    Assignee: Asahi Glass Company, Limited
    Inventor: Masaki Mikami
  • Patent number: 8927180
    Abstract: A method of manufacturing a mask may include forming initial ribs and removing edge portions of the initial ribs to form final ribs, each of which has a top width smaller than that of the initial rib. A space between the initial ribs may be smaller than a width of a slit limited by the final ribs.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Valeriy Prushinskiy, Wonsik Hyun, HeungYeol Na, Minsoo Kim, YoungShin Pyo, JaeMin Hong
  • Patent number: 8921014
    Abstract: A first embodiment is a lithography mask comprising a transparent substrate and a first molybdenum silicon nitride (MoxSiyNz) layer. The first MoxSiyNz layer is over the transparent substrate. A percentage of molybdenum (x) of the first MoxSiyNz layer is between 1 and 2. A percentage of silicon (y) of the first MoxSiyNz layer is between 50 and 55. A percentage of nitride (z) of the first MoxSiyNz layer is between 40 and 50. The first MoxSiyNz layer has an opening therethrough.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chue-San Yoo, Chun-Lang Chen
  • Patent number: 8877409
    Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Cheng Hsu, Chih-Tsung Shih, Chia-Jen Chen, Tsiao-Chen Wu, Shinn-Sheng Yu, Hsin-Chang Lee, Anthony Yen
  • Patent number: 8852853
    Abstract: A photo-mask is capable of preventing stain defects and a method for fabricating a liquid crystal display device using the photo-mask which achieves the same capability. The photo-mask includes a transparent substrate configured to transmit ultraviolet light and a light shielding layer configured to block ultraviolet light on a surface of the transparent substrate. The light shielding layer includes an absorption layer configured to absorb ultraviolet light.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki Hoon Kim, Ji-Yong Park, Jin-Suk Park, Sunghyuk Kim, Min-Chang Kim, Kyung Hyun Choi
  • Patent number: 8845908
    Abstract: A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imagable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imagable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imagable material. Other implementations are contemplated, including reticles which may be independent of method of use or fabrication.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott L. Light, Dan Millward, Yuan He, Kaveri Jain, Lijing Gou, Zishu Zhang, Anton deVilliers, Michael Hyatt, Jianming Zhou
  • Patent number: 8822104
    Abstract: A photomask is provided. The photomask is applied to a photolithography apparatus and includes a substrate with a mask pattern disposed thereon. The mask pattern includes at least one main pattern and a plurality of sub-resolution assistant features (SRAFs). The SRAFs are disposed around the at least one main pattern and separated from each other, wherein a distance between each of the SRAFs and the at least one main pattern is about 3 to 10 times a linewidth of the at least one main pattern. The photomask would result in an improved imaging quality on the wafer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: September 2, 2014
    Assignee: Nanya Technology Corporation
    Inventor: Wei-Cheng Shiu
  • Patent number: 8822103
    Abstract: A mask blank for manufacturing a transfer mask adapted to be applied with ArF excimer laser exposure light that has a transparent substrate and a light-shielding film formed into a transfer pattern. The light-shielding film has at least two-layers, one a lower layer composed mainly of a first material containing a transition metal, silicon, and nitrogen, and the other an upper layer composed mainly of a second material containing a transition metal, silicon, and nitrogen. A ratio of a first etching rate of the lower layer to a second etching rate of the upper layer is 1.0 or more and 5.0 or less in etching carried out by supplying a fluorine-containing substance onto a target portion and irradiating charged particles to the target portion. Another ratio satisfies the following formula CN??0.00526CMo2?0.640CMo=26.624.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 2, 2014
    Assignee: Hoya Corporation
    Inventors: Atsushi Kominato, Osamu Nozawa, Hiroyuki Iwashita, Masahiro Hashimoto
  • Patent number: 8784672
    Abstract: In a method of manufacturing a photomask pattern, a light-shielding layer pattern and an anti-reflective layer pattern are formed sequentially on a transparent substrate. Oxidation and nitridation processes are performed on a sidewall of the light-shielding layer pattern to form a protection layer pattern on a lateral portion of the light-shielding layer pattern.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Keun Oh, Dae-Hyuk Kang, Chan-Uk Jeon, Hyung-Ho Ko, Sung-Jae Han, Jung-Jin Kim
  • Patent number: 8778570
    Abstract: According to one embodiment, a photomask includes a substrate, a film portion, a pattern, and a plurality of detection marks. The film portion is provided on a surface of the substrate. The film portion has a light transmittance lower than light transmittance of the substrate. The pattern is provided in a surface of the film portion. The pattern is configured to be transferred to a transfer target. The plurality of detection marks is provided in the film portion, with intensity of light transmitted through the detection marks being suppressed so as to suppress transfer the detection marks to the transfer target.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Okuda, Yosuke Okamoto, Takaki Hashimoto, Hidenori Sato
  • Patent number: 8778569
    Abstract: There is provided a pellicle having a pellicle frame on which an adhesive layer for attaching the pellicle onto a photo mask is made from a room temperature curable two-part adhesive, so that a formation of the adhesive layer is carried out without heating. The room temperature curable two-part adhesive dispensed on the pellicle frame is not heated for curing.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: July 15, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Jun Horikoshi
  • Patent number: 8771527
    Abstract: A method of manufacturing an extreme ultraviolet (EUV) mask includes forming a first multi-layered thin film over a quartz substrate, forming a structure pattern over the first multi-layered thin film, and forming a second multi-layered thin film over the structure pattern and the first multi-layered thin film. The second multi-layered thin film is formed so that a periodicity of the second multi-layered thin film formed over the structure pattern is different from a periodicity of the second multi-layered thin film formed over the first multi-layered thin film.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae In Moon
  • Patent number: 8764995
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarizing process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber is substantially co-planar with the top surface of the hard mask layer.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsu Chang, Hung-Chun Wang, Boren Luo, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8765329
    Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min-Hung Cheng, Jing-Wei Shih, Wen-Han Chu, Cheng-Cheng Kuo, Hua-Tai Lin, Tsai-Sheng Gau, Ru-Gun Liu, Yu-Hsiang Lin, Shang-Yu Huang
  • Patent number: 8765328
    Abstract: An exposure mask used to transfer a pattern defined by exposure onto a wafer, includes: a substrate; a pattern formation region provided on the substrate, and having pattern elements formed therein, the pattern elements having a size not smaller than a resolution limit after being transferred onto the wafer; and a sub-pattern formation region provided on the substrate and having sub-pattern elements formed therein. The sub-pattern element has a size smaller than the resolution limit after being transferred onto the wafer, and the sub-pattern formation region is spaced from the pattern formation region by a distance having no optical proximity effect on the pattern.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomotaka Higaki
  • Patent number: 8677290
    Abstract: A method of forming a photolithography mask including forming a first linear non-dense feature on the mask and forming a plurality of parallel linear assist features disposed substantially perpendicular to the at least one linear non-dense design feature. In an embodiment, the photolithography mask further includes a first transverse linear assist feature disposed substantially transverse to the plurality of parallel linear assist features.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sung Yen, Kuei Shun Chen, Chien-Wen Lai, Cherng-Shyan Tsay
  • Patent number: 8663879
    Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Yong Seok Choi, Thomas J. Aton
  • Patent number: 8667432
    Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 4, 2014
    Assignee: Texas Instrument Incorporated
    Inventors: James Walter Blatchford, Yong Seok Choi, Thomas J. Aton