Abstract: A duty cycle calibration circuit includes delay, temperature compensation, differential, and phase adjustment units. The delay adjustment unit receives a single-ended input clock signal to be calibrated and an adjustment voltage and outputs a single-ended clock signal adjusted by the adjustment voltage. The temperature compensation adjustment unit determines the adjustment voltage output by the temperature compensation adjustment unit, and provides the adjustment voltage to the delay adjustment unit to eliminate the influence of the temperature on the duty cycle. The differential adjustment unit converts the single-ended clock signal into a differential clock signal, and adjusts delay of the differential clock signal.

Abstract: A device includes a filter circuit having both a transformer and a notch filter. The notch filter is formed via capacitive cross-coupling of windings of the transformer. The transformer includes a first winding with an input terminal and an output terminal and a second winding with an input terminal and an output terminal. The notch filter is formed by coupling a first capacitor between the input terminal of the first winding and the output terminal of the second winding, and by coupling a second capacitor between the output terminal of the first winding and the input terminal of the second winding.

Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.

Abstract: The present disclosure provides a phase shifter, an antenna and an electronic device. The phase shifter includes: a first dielectric substrate and a second dielectric substrate arranged opposite to each other, and an adjustable dielectric layer, a first electrode and a second electrode arranged between the first dielectric substrate and the second dielectric substrate, where the first electrode and the second electrode each extend in a first direction, and at least one of the first electrode and the second electrode includes a first sub-electrode and a second sub-electrode; the first sub-electrode is arranged on a side of the first dielectric substrate close to the adjustable dielectric layer, and the second sub-electrode is arranged on a side of the second dielectric substrate close to the adjustable dielectric layer, orthographic projections of the first sub-electrode and the second sub-electrode on the first dielectric substrate are partially overlapped with each other.

Abstract: The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

Abstract: Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

Abstract: A frequency multiplier includes a first digitally controlled delay line (DCDL) configured to receive a first clock signal and generate a second clock signal by changing a phase of the first clock signal, a multiplying delay-locked loop (MDLL) configured to generate a third clock signal by multiplying a frequency of the second clock signal, and a DCDL calibration circuit configured to receive the second clock signal and generate a gain signal for adjusting a gain of the first DCDL where a difference between a maximum delay and a minimum delay of the first DCDL is substantially equal to a period of the third clock signal.

Abstract: A directional coupler splits an input signal received by an input terminal into four signals to be output to output terminals. The directional coupler includes couplers and phase shifters. The coupler is connected to the input terminal and splits the input signal into two signals to be output to terminals. The coupler splits a signal from the terminal into two signals to be output to the output terminals. The coupler splits a signal from the terminal into two signals to be output to the output terminals. The phase shifter is connected between the terminal and the coupler and advances the phase of the signal from the terminal. The phase shifter is connected between the terminal and the coupler and delays the phase of the signal from the terminal. The phase difference between output signals of the phase shifters is 180°±10°.

Abstract: Disclosed are a frequency multiplier, a signal transmitter and a radar chip. The frequency multiplier includes a signal generator that is configured to receive an FMCW signal and output a square wave signal at a frequency same as a frequency of the FMCW signal; and a third harmonic amplifier that is coupled to the signal generator and is configured to amplify a third harmonic wave in the square wave signal and output a frequency-tripled FMCW signal. The above-mentioned solution can improve the generation efficiency of the frequency-tripled signal.

Abstract: Aspects of this disclosure relate to a bulk acoustic wave device that includes a multi-layer raised frame structure. The multi-layer raised frame structure includes a first raised frame layer positioned between a first electrode and a second electrode of the bulk acoustic wave device. The first raised frame layer has a lower acoustic impedance than the first electrode. The first raised frame layer and the second raised frame layer overlap in an active region of the bulk acoustic wave device. Related filters, multiplexers, packaged modules, wireless communication devices, and methods are disclosed.

Abstract: Provided are a resonator and a filter that exhibit preferable characteristics. This resonator has: a via electrode which is formed within a dielectric substrate; a plurality of shielded conductors which are formed in the dielectric substrate so as to surround the via electrode; and a strip line which is connected to the via electrode inside the dielectric substrate and which is disposed so as to at least face the shielded conductors, wherein, of the plurality of shielded conductors, one that is connected to a short-circuited end of the via electrode is capacitatively coupled, across a spacing, to a first input/output terminal and a second input/output terminal.

Abstract: A filter circuit includes a pair of balanced input ports, a pair of balanced output ports, first and second resonators provided in parallel between the pair of balanced input ports and the pair of balanced output ports in a circuit configuration, a first capacitor connected in parallel to the first resonator, and a second capacitor connected in parallel to the second resonator. The first and second resonators are magnetically coupled to each other and electrically connected to each other. The first and second capacitors are not electrically connected to ground.

Abstract: A duty cycle calibration circuit and method solves duty cycle calibration without single ended I/O signals. The calibration circuit includes driving circuit and voltage divider units, a low-pass filter, voltage controlled oscillator, digital processing unit, and duty cycle adjustment unit.

Abstract: A pulse filter circuit is configured to eliminate pulses that are less than a specified duration and pass those that are greater than the specified duration. A buffer receives a signal and applies the buffered signal to a resistance-capacitance charging-discharging circuit (e.g., RC filter). When the output of the RC filter has, in response to the buffered signal, charged or discharged, as appropriate, to cause the output of a slicer to change, logic circuitry controls switching circuitry to pull the output of the RC filter to be fully charged or discharged, respectively. In this manner, pulses that are too short to charge/discharge the RC filter enough to cross the threshold of the slicer do not reach the slicer circuit output, but pulses that are long enough to cross the slicer threshold are transmitted by the slicer.

Abstract: In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.

Abstract: Aspects of the subject disclosure may include, for example, a frequency divider, comprising a plurality of delay devices arranged to receive input clocks and generate output clocks, wherein one or more of the delay devices comprises a first transconductance element configured to receive a first input and provide a first output, a second transconductance element configured to receive a second input and provide a second output, a first feedforward transconductance element that cross couples the first input and the second output, and a second feedforward transconductance element that cross couples the second input and the first output. Other embodiments are disclosed.

Abstract: A 6 GHz Wi-Fi bandpass filter includes a ladder filter circuit with two or more shunt transversely-excited film bulk acoustic resonators (XBARs) and two or more series XBARs. Each of the two or more shunt XBARS includes a diaphragm having an LN-equivalent thickness greater than or equal to 310 nm, and each of the two or more series XBARS includes a diaphragm having an LN-equivalent thickness less than or equal to 305 nm.

Abstract: A power divider and an electronic device are provided. The power divider includes: a main port having an input characteristic admittance; a first output port having a first characteristic admittance; a second output port having a second characteristic admittance, where the second and the first characteristic admittances have a predetermined ratio relationship; a first adjustment branch coupled between the main port and the first output port; and a second adjustment branch coupled between the main port and the second output port. The input characteristic admittance is a sum of admittances presented by the first and second adjustment branches at the main port. The admittance presented by the first adjustment branch at the main port and the admittance presented by the second adjustment branch at the main port are adjustable and the input characteristic admittance is enabled to be equal to a sum of the first and the second characteristic admittances.

Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.

Abstract: An electronic device may include isolation circuitry coupled between a transmitter, a receiver, and one or more antennas. The isolation circuitry may include a 90 degree hybrid coupler configured receive a transmission (TX) signal from the transmitter, split the TX signal into a first portion and a second portion, and phase-shift a portion such that the portions are +90 degrees out-of-phase. The isolation circuitry may include phase shifters that phase-shift the portions such that the portions are in-phase prior to propagating to the antenna. The phase shifters may receive a first portion and a second portion of a receiver (RX) signal from splitter circuitry. The phase shifters may phase-shift the portions such that the portions are out-of-phase by ?90 degrees. The 90 degree hybrid coupler may phase-shift the first portion and/or the second portion such that the portions are in-phase and constructively combine prior to propagating to the receiver.