Patents Examined by John W Poos
  • Patent number: 11405026
    Abstract: Embodiments of the present disclosure provide systems and methods of reducing the EMI effect generated by such analog blocks. By varying the clock frequency in time of oscillators used by such analog blocks, the EMI energy may be spread over a wide spectrum range thereby reducing the peak energy for the main frequency. To achieve this, the oscillator frequency is directly varied using analog mechanisms. The mechanisms may be based on a synchronized method for increasing/decreasing the current that is charging/discharging the oscillator capacitor. The frequency variation may be achieved by analog control of the extra charge/discharge current.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies LLC
    Inventors: Oleg Dadashev, Yoram Betser
  • Patent number: 11394384
    Abstract: Radio-frequency switches and related circuits are disclosed. In some embodiments, a switching device can include a series arm having transistors implemented in a stack configuration between first and second nodes. The switching device can further include a shunt arm having transistors implemented in a stack configuration between the first node and a ground node. The switching device can further include a bias architecture having a series arm bias circuit and a shunt arm bias circuit. The series arm bias circuit can be configured to bias the transistors of the series arm and include a gate-gate resistor that couples each pair of neighboring transistors. The shunt arm bias circuit can be configured to bias the transistors of the shunt arm and include a gate-gate resistor that couples each pair of neighboring transistors.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 19, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Guillaume Alexandre Blin
  • Patent number: 11383177
    Abstract: Method, modules and a system formed by connecting the modules for controlling payloads are disclosed. An activation signal is propagated in the system from a module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to external power source such as AC power.
    Type: Grant
    Filed: August 16, 2020
    Date of Patent: July 12, 2022
    Assignee: May Patents Ltd.
    Inventor: Yehuda Binder
  • Patent number: 11387813
    Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 12, 2022
    Assignee: MEDIATEK INC.
    Inventors: Hsiu-Hsien Ting, Po-Chun Huang, Yu-Li Hsueh
  • Patent number: 11381229
    Abstract: A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit and a signal generation circuit. The control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the frequency control word, and the spread spectrum output signal corresponds to the frequency control word.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: July 5, 2022
    Assignees: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangye Wei, Liming Xiu, Yuhai Ma
  • Patent number: 11380412
    Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: July 5, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 11368142
    Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to provide an integrator signal indicating substantially an integral of a corrected clock signal. The amplifier circuit is configured to be disabled responsive to a detection that an input clock signal is disabled. The amplifier circuit includes a first amplifier input terminal and a second amplifier input terminal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal responsive to the detection that the input clock signal is disabled. A method of correcting a duty-cycle of an input clock signal includes adjusting a corrected duty-cycle of the corrected clock signal responsive to a first error signal and a second error signal from the amplifier circuit.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
  • Patent number: 11355948
    Abstract: Embodiments describe a wireless charging system including an accessory device and a host device. The host device can include a housing having a charging surface and power transmitting circuitry coupled to a power source. The power transmitting circuitry can include an inductive transmitter coil configured to receive a first power and generate magnetic field, an amplifier coupled to the inductive transmitter coil and configured to output the first power to the inductive transmitter coil, an output sensor coupled to the inductive transmitter coil and configured to measure the first power to the inductive transmitter coil, and a power tracking controller coupled to the sensor probe. The power tracking controller can be configured to receive measurement of the first power, and generate a control signal based on the measured first power to modify an output impedance of the amplifier to output a second power different from the first power.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 7, 2022
    Assignee: Logitech Europe S.A.
    Inventors: Maxim Vlasov, Laurent Plancherel
  • Patent number: 11340279
    Abstract: A device for detecting stray electrical currents in fluid mediums comprises at least two probes for partially disposing in a fluid medium and a control unit. The control unit comprises at least one analog-to-digital signal converter in electrical communication with at least one of the probes, at least one audio-visual alarm, and a processor operably coupled to the at least one converter and to the at least one audio-visual alarm. The processor is operable to measure an electrical potential difference between the two probes, to calculate at least one frequency-dependent characteristic associated with a plurality of said measurements, and to transmit an alert signal if the at least one frequency-dependent characteristic satisfied a threshold. Advantageously, by monitoring for the frequency, the device more consistently and more reliably detects the presence of stray alternating currents.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 24, 2022
    Assignee: Marine Co. Systems, LLC
    Inventors: Matthew Bruce Fitzgerald, Amar Thors, Roger Alan Miller, John David Cook, Daniel James Myers
  • Patent number: 11342927
    Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 24, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Younghyun Lim, Yiwu Tang, Dongmin Park, Yunliang Zhu, Mustafa Keskin, Yue Chao
  • Patent number: 11334110
    Abstract: In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: May 17, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Xiaobin Yuan, Aida Varzaghani, Irina Gavshina, Mouna Safi-Harab
  • Patent number: 11336289
    Abstract: According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 17, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hiroaki Kojima
  • Patent number: 11336269
    Abstract: An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dalhee Lee, Byounggon Kang
  • Patent number: 11335538
    Abstract: The invention relates to a filter unit for filtering multiple pulse signals comprising a number of filter circuits, which are connected in parallel. Each filter circuit comprises an input and an output, wherein the input is configured to receive an amplitude of an input signal and the output is configured to activate an output signal. Each filter circuit has an allocated filter level and further comprises a pulse level detection circuit configured to detect a change of state of a pulse level of the input signal. The change of state comprises a transition from a first pulse level to a second pulse level and if the pulse level corresponds to the allocated filter level of the filter circuit the output of said filter circuit is activated.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 17, 2022
    Assignee: COMET AG PLASMA CONTROL TECHNOLOGIES
    Inventors: Manuel vor dem Brocke, Roland Schlierf
  • Patent number: 11329639
    Abstract: A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 10, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Chiu Keung Tang, Zhiqin Chen
  • Patent number: 11329635
    Abstract: Techniques for controlling a power converter with a control signal and circuitry configured to translate the control signal into one or more pulse modulated drive signal(s) to operate the power converter. The translation circuitry may receive the control signal, extract frequency information, duty cycle, dead time, and other information from the control signal, and output at least one pulse modulated drive signal, based on the extracted information, to a driving stage that may operate the power converter. The control signal may be a digital signal that includes rising edges and falling edges. The edges of the first type may define the frequency information. The edges of the second type may define other information extracted by the translation circuitry, e.g., duty cycle, dead time and so on. In some examples the power converter may be a resonant power converter.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Mathias Dahlhaus, Kevin Pluch, Jens Barrenscheen
  • Patent number: 11323102
    Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel IP Corporation
    Inventors: Michael Kalcher, Daniel Gruber, Francesco Conzatti, Patrizia Greco
  • Patent number: 11323109
    Abstract: A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Surya Theja Golakonda, Robin Gupta
  • Patent number: 11314070
    Abstract: A method for timing procedures in a microscope system, which has a plurality of microscope modules configured to carry out various processes, provision is made for a clock signal to be provided to all microscope modules by a central clock generator and for the clock signal to be modulated by a clock modulation circuit in order to produce a defined clock-pulse number. The microscope modules define a start time for carrying out a process by way of the clock-pulse number, carrying out the process as soon as the clock-pulse number is reached. Moreover, a corresponding microscope system is described.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 26, 2022
    Assignee: Carl Zeiss Microscopy GmbH
    Inventors: Mirko Liedtke, Andreas Kühm, Nico Presser, Burkhard Roscher, Christian Kämmer
  • Patent number: 11316503
    Abstract: A phase and/or amplitude modulation device includes a TORP signal generator and, during a phase modulation or a phase and amplitude modulation, a generator of a phase-modulated periodic signal of frequency FPRP applied to a control input of the power supply circuit of the TORP signal generator. The device may also include, during an amplitude modulation or a phase and amplitude modulation, 2P TORP generators, a thermometric code generator on 2P bits coding an amplitude modulation, a TORP generator control circuit, applying or not, to the control input of the TORP generator power supply, the periodic signal of frequency FPRP depending on the bits of the thermometric code signal, and a processing circuit coupled to the outputs of the TORP generators, and configured to produce a linear combination of signals outputted by the TORP generators.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 26, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: José-Luis Gonzalez Jimenez