Abstract: A switch monitoring device includes a constant current source which supplies a current to an input line or extracts a current from the input line, a switch which connects the input line to a supply voltage or to a ground voltage, a comparator which compares a voltage on the input line with a reference voltage, a logic which receives an output voltage of the comparator, a base current source which generates a base current, and a bias current circuit which generates a bias current by adjusting the base current as a base in accordance with a current control signal from the logic and the output voltage of the comparator. The constant current source generates a current by adjusting the bias current as a base.
Abstract: An output stage circuit of a power conversion circuit includes a first power switch, a driving circuit, a first current source, a second current source and a combining circuit. The first power switch is coupled to a second terminal of a bootstrap capacitor. The driving circuit is coupled to the first terminal of the bootstrap capacitor and the first power switch and provides a control signal to the first power switch. The first current source generates a first current according to the control signal. The second current source generates a second current according to a reference voltage which is a first voltage at the first terminal or a second voltage at the second terminal. The combining circuit, coupled to the driving circuit, the first current source and the second current source, generates a switch operation indicating signal to the driving circuit according to the first current and second current.
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
December 18, 2019
Date of Patent:
February 9, 2021
STMICROELECTRONICS S.r.l., STMICROELECTRONICS, Inc., STMICROELECTRONICS (ALPS) SAS
Vanni Poletto, David F. Swanson, Giovanni Luca Torrisi, Laurent Chevalier
Abstract: A power conversion device includes a transformer, a first electrical switch, a second electrical switch, at least one balanced capacitor, at least one voltage-stabilizing capacitor, and a power-providing circuit. The first electrical switch, the second electrical switch, the balanced capacitor, and the voltage-stabilizing capacitor are connected to the primary side of the transformer, and the secondary side of the transformer is connected to the power-providing circuit. The primary side has a first terminal, a second terminal, and a third terminal therebetween. The first electrical switch and the second electrical switch are respectively connected to a high-voltage terminal and a low-voltage terminal, and the voltage-stabilizing capacitor is connected between the two voltage terminals. One end of the balanced capacitor is connected to the third terminal, and another end of the balanced capacitor is connected to the voltage-stabilizing capacitor or the voltage terminals.
December 20, 2019
Date of Patent:
February 9, 2021
Suzhou Mean Well Technology Co., Ltd., Mean Well (Guangzhou) Electronics Co., Ltd.
Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.
November 11, 2019
Date of Patent:
February 2, 2021
SAMSUNG ELECTRONICS CO., LTD, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Jae-Woo Seo, Youngsoo Shin, Jinwook Jung
Abstract: Systems and techniques are provided for beamforming for wireless power transfer. A position of a second wireless power transfer device relative to a first wireless power transfer device may be determined. A beam may be simulated as being transmitted from the position of the second wireless power transfer device. Phases of a wave front of the simulated beam that would be received by elements of the first wireless power transfer device may be determined. A control signal for each of the elements for which phases were determined may be generated based on the determined phase of the wave front that would be received at the element. The control signal for each of the elements for which phases were determined may be supplied to the elements for which phases were determined. A waveform may be transmitted from the elements for which phases were determined based on the supplied control signal.
Abstract: The present invention provides a circuit including an output buffer, a tracking circuit and a pre-driver, where the output buffer includes at least one P-type transistor and at least one N-type transistor, the at least one P-type transistor is coupled between a supply voltage and a pad, and the at least one N-type transistor is coupled between a ground voltage and the pad. In the operations of the circuit, the tracking circuit is configured to generate a tracking signal control signal according to a voltage level at the pad, and the pre-driver is configured to generate a control signal to control the at least one P-type transistor or the at least one N-type transistor according to the tracking signal.
Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.
Abstract: An electronic circuit of the embodiments includes at least one first n-type transistor, at least one first p-type transistor, a supply circuit, a detection circuit, and a control circuit. The supply supplies current to a control terminal of a semiconductor switching element. The detection circuit acquires a value associated with a voltage at a first terminal of the semiconductor switching element. The control circuit causes one type of transistors of the first n-type transistors and the first p-type transistors to be in the non-driven state and causing at least one of the other type of transistors to be in the driven state, at least based on the value associated with the voltage. The first n-type transistor is electrically connected to a reference potential and the control terminal, and the first p-type transistor is electrically connected to a power supply potential and the control terminal.
Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.
Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
Abstract: The present disclosure relates to a power management circuit (PMC) with a dual charge pump (DCP) structure. The DCP structure includes a first switch network having a first capacitor, a second switch network having a second capacitor, and a connection switch coupled between the first switch network and the second switch network. Herein, the first capacitor and the second capacitor are electrically coupled in series between a battery terminal and a ground terminal or electrically coupled in parallel between the battery terminal and the ground terminal during a charging phase. The first capacitor and the second capacitor are electrically coupled in series between the battery terminal and a pump output terminal, or electrically coupled in parallel between the battery terminal and the pump output terminal, or electrically coupled in parallel between the ground terminal and the pump output terminal during a discharging phase.
Abstract: In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further includes a multiplexer including a first input, a second input, and an output, wherein the first input of the multiplexer is configured to receive a first clock signal, the second input of the multiplexer is configured to receive a second clock signal, and the output of the multiplexer is coupled to the clock input of the bias generator.
Abstract: A buffer circuit includes a current mode circuit configured to generate output signals by converting a current path depending on input signals and configured to correct a swing width of the output signals by adjusting a current amount depending on a level of a compensation signal. The buffer circuit also includes a compensation signal generation circuit configured to detect a swing width variation of the output signals and configured to generate the compensation signal for correcting a swing width of the output signals to conform to a target value, depending on a detected swing width.
Abstract: Provided are embodiments for a circuit including a DC-DC converter for current controlled solenoid drive, the circuit includes a constant current source; a charge pump circuit comprising a plurality of stages. Each stage includes a capacitor configured to be charged to a predetermined voltage; a current source operable to charge the capacitor; a switch; and a controller that is configured to control switching of the switch for each of the plurality of stages based at least in part on an output current of the charge pump. Also, provided are embodiments of a method for operating a DC-DC converter for current controlled solenoid drive.
Abstract: Aspects of the present disclosure address a slew rate controlled driver. The slew rate controlled driver includes an amplifier with a capacitive feedback loop and a current generator capable of producing a current that is proportional to on-chip capacitance. The current generator is implemented using a switched capacitor and supplies the driver with a current that is proportional to the capacitance of the switched capacitor. By supplying the driver with current that is proportional to the capacitance of the switched capacitor, the slope of the output signal of the driver is proportional to the ratio of the switched capacitance and a capacitance of the driver's capacitive feedback loop.
Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.
Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.
Abstract: An electronic switch includes a first NMOS transistor connected between a positive input terminal and an output terminal; a first diode, a second resistor, a first capacitor, and a third switching element sequentially connected in series between a drain of the first NMOS transistor and a negative input terminal; a first resistor connected between a positive input terminal and a node between the first capacitor and the third switching element; a third resistor connected between a gate of the first NMOS transistor and a node between the second resistor and the first capacitor; and a second capacitor, a second diode, and a fourth resistor connected in parallel between a source of the first NMOS transistor and a node between the third resistor and the gate of the first NMOS transistor.
Abstract: A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a high-swing mode, a low-swing mode with equalization, and a low-swing mode without equalization. Transmitter circuitry provided in this way removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth, flexibility, and scalability demands.