Abstract: An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.
Abstract: Battery module communication system with improved enclosure sealing is disclosed. When applied to an electric vehicle, a battery data communication system disclosed herein includes module enclosures having partial transformers, such as coils, contained inside the enclosures having inter-module interfaces. The inter-module interfaces can engage with one another to form transformers without the module enclosures having wire holes to connect data communication circuits contained in the respective module enclosures.
Abstract: Active feedback is used with two electrodes of a four-electrode capacitive-gap transduced wine-glass disk resonator to enable boosting of an intrinsic resonator Q and to allow independent control of insertion loss across the two other electrodes. Two such Q-boosted resonators configured as parallel micromechanical filters may achieve a tiny 0.001% bandwidth passband centered around 61 MHz with only 2.7 dB of insertion loss, boosting the intrinsic resonator Q from 57,000, to an active Q of 670,000. The split capacitive coupling electrode design removes amplifier feedback from the signal path, allowing independent control of input-output coupling, Q, and frequency. Controllable resonator Q allows creation of narrow channel-select filters with insertion losses lower than otherwise achievable, and allows maximizing the dynamic range of a communication front-end without the need for a variable gain low noise amplifier.
December 4, 2018
Date of Patent:
January 7, 2020
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Clark T.-C. Nguyen, Thura Lin Naing, Tristan O. Rocheleau
Abstract: An electronic circuit providing a linear keypad and an apparatus comprising such electronic circuit are provided. Methods for detecting that a button of a linear keypad is being pressed and for determining which button is being pressed are also provided. A method for calibrating an apparatus comprising a linear keypad to enable the subsequent determination by the apparatus of which button of the linear keypad is being pressed is also provided.
Abstract: An automatic power supply system is electrically coupled to a component to be tested. The automatic power supply system includes a power array and a controller. The power array includes a plurality of power channels, and provides power supplies through the plurality of power channels. The component to be tested is electrically coupled to a first power channel of the plurality of power channels and receives a power supply through the first power channel. The controller is electrically coupled to the power array, and calculates a power of the power supply received by the component to be tested. The controller adjusts a power specification of the power supply provided through the first power channel according to the power.
Abstract: A bi-directional switch circuit includes first and second transistors having their control electrodes coupled at a first common node and the current paths coupled at a second common node in an anti-series arrangement. First and second electrical paths coupled between the first common node and the first and second transistors, respectively, include first and second switches switchable between a conductive state and a non-conductive state. A third electrical path between the first and second common nodes includes a third switch switchable between a conductive state and a non-conductive state. The third switch is coupled with the first and second switches by a logical network configured to switch the third switch to the conductive state with the first and second switches switched to the non-conductive state, and to the non-conductive state with either one of the first and second switches switched to the conductive state.
Abstract: Disclosed herein are examples of wireless charging transmitters and methods. As one example, a wireless charging transmitter includes a sensor to detect the presence of a receiver device and/or a living being and the sensor generates data according to the presence detected. The wireless charging transmitter also includes an array of antennas configured to transmit power waves to the receiver device and a surface layer that is adjacent to the array of antennas. The transmitted power waves converge to form a constructive interference pattern at a non-zero distance from the surface layer. The non-zero distance being based on the sensor data. Further, the phases and amplitudes of the transmitted power waves are determined based, at least in part, on the sensor data.
Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.
December 26, 2018
Date of Patent:
December 24, 2019
TEXAS INSTRUMENTS INCORPORATED
Eric Paul Lindgren, Arvind Sridhar, Jayawardan Janardhanan
Abstract: A signal level converter includes a bias generating circuit that generates a bias voltage, and a level shifter circuit that converts a lower voltage signal into a higher voltage signal in response to the bias voltage. The bias generating circuit includes a replica circuit that controls an on-current of the level shifter circuit in response to the bias voltage output from an operational amplifier.
Abstract: Provided is an energy conversion and storage apparatus using an electronic wave. The device comprises: a rectifier which rectifies an alternating current generated by converting an electronic wave inputted from the outside; and storage which receives and stores the rectified alternating current and is grounded.
Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.
Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.
Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.
August 14, 2018
Date of Patent:
December 17, 2019
Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
Jae-Woo Seo, Youngsoo Shin, Jinwook Jung
Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.
Abstract: According to one embodiment, a charge pump is configured to generate a negative potential at an output node. A first transistor and a first resistor are coupled in series in order between a first node and a second node. A second resistor is coupled between the second node and the output node. A second transistor and a third resistor are coupled in series in order between the first node and a third node. A fourth resistor is coupled between the third node and the output node. A third transistor is coupled between a fourth node and the output node, and coupled to the second node and the third node at a gate.
Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
December 27, 2018
Date of Patent:
December 3, 2019
TEXAS INSTRUMENTS INCORPORATED
Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.
Abstract: A method for tuning a current source of a digitally controlled oscillator having an LC tank having a tunable capacitor bank includes: determining a specific threshold according to a resolution of a bit number of the tunable capacitor bank; configuring a current flowing through the current source at a first current level; tuning the current flowing through the current source from the first current level to a lower current level; comparing a variation of a digital value of the tunable capacitor bank with the specific threshold, the digital value corresponding to the lower current level; and determining that a current level required by the digitally controlled oscillator is decreased down to the lower current level and then configuring the current flowing through the current source at the lower current level if the variation of the digital value is smaller than the specific threshold.
Abstract: A method for controlling consumers of a low-voltage on-board electrical system of a motor vehicle reduces, when it is identified that a high-current consumer is connected, the current consumption of another consumer by an amount that corresponds to the current consumption of the high-current consumer. A control apparatus for controlling consumers of a low-voltage on-board electrical system of a motor vehicle is also provided.
Abstract: A safety gas valve relay driving circuit for an HVAC system includes a gas valve relay including an output for selectively enabling and disabling a gas valve in an HVAC system according to an energization state of the gas valve relay, and a charge pump circuit to control energization of the gas valve relay. The charge pump circuit includes a charge pump capacitor. The driving circuit also includes first and second inputs for receiving first and second driving signals from at least one controller, a low-pass filter coupled between the first input and the charge pump circuit to filter the received first driving signal, and a high-pass filter watchdog circuit coupled between the second input and the charge pump circuit to filter the received second driving signal. Example methods of driving a gas valve relay for an HVAC system are also disclosed.