Patents Examined by John W Poos
  • Patent number: 10505443
    Abstract: According to one embodiment, a charge pump is configured to generate a negative potential at an output node. A first transistor and a first resistor are coupled in series in order between a first node and a second node. A second resistor is coupled between the second node and the output node. A second transistor and a third resistor are coupled in series in order between the first node and a third node. A fourth resistor is coupled between the third node and the output node. A third transistor is coupled between a fourth node and the output node, and coupled to the second node and the third node at a gate.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 10, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hironori Nagasawa
  • Patent number: 10504569
    Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 10, 2019
    Assignee: INVECAS TECHNOLOGIES PVT. LTD
    Inventors: Gyan Prakash, Nidhir Kumar, Muniswara Reddy Vorugu
  • Patent number: 10498344
    Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
  • Patent number: 10491223
    Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hangi Jung, Hun-Dae Choi, Juho Jeon
  • Patent number: 10491226
    Abstract: A method for tuning a current source of a digitally controlled oscillator having an LC tank having a tunable capacitor bank includes: determining a specific threshold according to a resolution of a bit number of the tunable capacitor bank; configuring a current flowing through the current source at a first current level; tuning the current flowing through the current source from the first current level to a lower current level; comparing a variation of a digital value of the tunable capacitor bank with the specific threshold, the digital value corresponding to the lower current level; and determining that a current level required by the digitally controlled oscillator is decreased down to the lower current level and then configuring the current flowing through the current source at the lower current level if the variation of the digital value is smaller than the specific threshold.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 26, 2019
    Assignee: Audiowise Technology Inc.
    Inventor: Lien-Sheng Wei
  • Patent number: 10480811
    Abstract: A safety gas valve relay driving circuit for an HVAC system includes a gas valve relay including an output for selectively enabling and disabling a gas valve in an HVAC system according to an energization state of the gas valve relay, and a charge pump circuit to control energization of the gas valve relay. The charge pump circuit includes a charge pump capacitor. The driving circuit also includes first and second inputs for receiving first and second driving signals from at least one controller, a low-pass filter coupled between the first input and the charge pump circuit to filter the received first driving signal, and a high-pass filter watchdog circuit coupled between the second input and the charge pump circuit to filter the received second driving signal. Example methods of driving a gas valve relay for an HVAC system are also disclosed.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 19, 2019
    Assignee: EMERSON ELECTRIC CO.
    Inventors: Cuiyun Chen, Yindan Zhang, Yonglong Hu
  • Patent number: 10483809
    Abstract: Foreign substance detection can be performed with a simple configuration in a power transmission system. A power transmitting apparatus that wirelessly transmits power to a power receiving apparatus, the power transmitting apparatus comprises: determination means for, in a case where an initial impedance value and the detected output impedance value do not match and there is no change in the output impedance value between before and after the transmission of a predetermined detection signal, determining that a foreign substance is present within a predetermined power transmission range, and, in a case where the initial impedance value and the detected output impedance value do not match and there is a change in the output impedance value between before and after the transmission of the predetermined detection signal, determining that a power receiving apparatus is present within the predetermined power transmission range.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: November 19, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takahiro Shichino
  • Patent number: 10479299
    Abstract: A method for controlling consumers of a low-voltage on-board electrical system of a motor vehicle reduces, when it is identified that a high-current consumer is connected, the current consumption of another consumer by an amount that corresponds to the current consumption of the high-current consumer. A control apparatus for controlling consumers of a low-voltage on-board electrical system of a motor vehicle is also provided.
    Type: Grant
    Filed: July 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Volkswagen Aktiengesellschaft
    Inventor: Kai Bühring
  • Patent number: 10466739
    Abstract: A semiconductor device includes a clock selection block selecting a first or a second input clock as a reference clock based on a phase detection signal; a clock generation circuit outputting first to Nth sampling clocks by distributing the reference clock to first to Nth clock paths, and outputting a first training signal by delaying a test pulse through one clock path during a training operation; a data input circuit sampling input data based on the first and second input clocks and one sampling clock outputted through the same clock path as the first training signal among the first to Nth sampling clocks; and a training circuit delaying the test pulse by a reference delay value to output a second training signal, and comparing a phase of the first training signal with a phase of the second training signal to generate the phase detection signal, during the training operation.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Ji-Eun Heo
  • Patent number: 10461728
    Abstract: A semi-controllable device driving method and apparatus and a hybrid device of the present disclosure belong to the electrical field, and are particularly a driving method, with no driving dead zone or with an extremely small driving dead zone, that is applicable to a semi-controllable device such as a thyristor; a semi-controllable driving apparatus, with no conduction dead zone or with an extremely small conduction dead zone, that is applicable to a driving loop of a semi-controllable device such as a thyristor; and a hybrid device with no conduction dead zone or with an extremely small conduction dead zone.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: October 29, 2019
    Inventor: Qiaoshi Guo
  • Patent number: 10459501
    Abstract: A method and apparatus for performing operations of an electrical device, whereby the apparatus performs operations during operation of a clock producing a clock signal, asserts a reset of components performing operations for the electrical device, stops the clock through a reset generation block for a number N cycles and performs the reset of operations during the stopping of the clock through the reset generation block for the number N cycles.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventor: Atif Hussain
  • Patent number: 10451659
    Abstract: A detection circuit of an electronic device includes a resistance detecting circuit and a voltage supplying circuit, wherein the detecting circuit is coupled to an input circuit which is coupled to the electronic device and comprises a plurality of resistors respectively coupled to a plurality of switches, wherein the resistance detecting circuit is arranged to detect whether the input circuit has a resistance variation and generate a detecting signal indicative of the resistance variation; and the voltage supplying circuit is coupled to the resistance detecting circuit to supply a first voltage signal, wherein the voltage supplying circuit receives the detecting signal, and selectively switches the first voltage signal to a second voltage signal according to the detecting signal; wherein the resistance detecting circuit determines whether at least one of the plurality of switches is closed according to the second voltage signal.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 22, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Pin Chang, Tsung-Peng Chuang, Wei-Chieh Wang
  • Patent number: 10453865
    Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10454486
    Abstract: The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal of the processing core and comprising a frequency locked loop having: a digitally controlled oscillator configured to generate the variable frequency clock signal; and a controller (614) configured to generate a digital control signal (C_FREQ), wherein the controller is configured to implement a frequency transition of the variable frequency clock signal from a first frequency to a second lower frequency by generating: a first value of the digital control signal (C_FREQ) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency lower than the second frequency; and further values of the digital control signal (C_FREQ).
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 22, 2019
    Assignee: COMMISSARIAT ÀL'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Ivan Miro Panades
  • Patent number: 10453507
    Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwoo Jeong, Hwaseok Oh, JinHyeok Choi
  • Patent number: 10454463
    Abstract: Apparatus and associated methods relate to a dynamic quantizer circuit including a tail voltage supply magnitude (VTAIL) distinct from a general supply voltage (Avcc/Avss), VTAIL providing power to a tail clock buffer to generate tail clock signals to tail devices. In an illustrative example, a compensation processor may control a regulator producing a determined VTAIL value in response to one or more parametric signals, for example, the Avcc voltage value, a circuit temperature and a transistor speed process (TSP). The TSP signal may be determined, for example, by process-dependent circuit devices. The compensation processor may be, for example, configured to lower VTAIL in response to detecting a worst-case RMS noise corner, or to raise VTAIL in response to detecting a worst-case clock-to-q corner. Various adjustable VTAILs may be configured to continuously optimize RMS noise, offset and speed performance with low power consumption in various quantizers over process, voltage and/or temperature.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 22, 2019
    Assignee: XILINX, INC.
    Inventor: James Hudner
  • Patent number: 10447034
    Abstract: Method, modules and a system formed by connecting the modules for controlling payloads are disclosed. An activation signal is propagated in the system from a module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to external power source such as AC power.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 15, 2019
    Inventor: Yehuda Binder
  • Patent number: 10438933
    Abstract: A semiconductor device includes: a first semiconductor die and a second semiconductor die connected on the first semiconductor die, in which the first semiconductor die includes buffers in a second-stage configuration to an Nth-stage configuration (N being an integer of 3 or more) in a clock tree structure, and the second semiconductor die includes a logic circuit electrically connected to the buffer in the Nth-stage configuration.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 8, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hironori Kawaminami
  • Patent number: 10432179
    Abstract: We disclose frequency doublers for use in millimeter-wave devices. One such frequency doubler comprises at least one passive mixer comprising at least one of the following: at least one transistor configured to receive a back gate voltage; at least one first input driver circuit; and two second input driver circuits. We also disclose a method comprising determining a target output voltage of a frequency doubler comprising at least one passive mixer comprising at least one transistor configured to receive a back gate voltage; determining an output voltage of the frequency doubler; increasing a back gate voltage of the at least one transistor, in response to determining that the output voltage is below the target output voltage; and decreasing the back gate voltage of the at least one transistor, in response to determining that the output voltage is above the target output voltage.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Patent number: 10432255
    Abstract: A transmission device of the present disclosure includes: a driver unit that transmits a data signal with use of a first voltage state, a second voltage state, and a third voltage state interposed between the first voltage state and the second voltage state, and is configured to make a voltage in the third voltage state changeable; and a controller that changes the voltage in the third voltage state to cause the driver unit to perform emphasis.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventor: Hiroaki Hayashi