Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.

Abstract: A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a clock cycle. The second slave stage generates an inverted output signal during the rising edge of the clock cycle. The output signal and the inverted output signal are available concurrently.

Abstract: A transmitter may inductively transfer power to a device via a relay. The transmitter may comprise circuitry configured to measure a current or voltage and reconfigure the transmitter with an operating frequency or duty cycle based on a measured change in the current or voltage within a time period. The measured change in the current or voltage within the time period may be caused by a removal of the device or an addition of a new device. The time period may be 200 usec or less.

Abstract: An embodiment apparatus comprises a switching-type output power stage, a modulator circuit configured for carrying out a pulse-width modulation and converting an electrical input signal into an input signal pulsed between two electrical levels, having a mean value proportional to the amplitude of the input signal, and a circuit arrangement for controlling saturation of an output signal supplied by the switching-type output power stage. The circuit arrangement comprises a pulse-remodulator circuit, between the output of the modulator circuit and the input of the switching-type output power stage, that is configured for supplying, as a driving signal to the switching-type output power stage, a respective modulated signal pulsed between two electrical levels, measuring a pulse width as pulse time interval elapsing between two consecutive pulsed-signal edges of the pulsed input signal, and, if the measurement indicates that the latter is below a given minimum value, remodulating the pulsed input signal.

Abstract: A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

Abstract: An apparatus converts an AC power panel into a persistent DC power panel with a persistent power switch. The persistent power switch includes a removable power unit for coupling to the AC power switch in order to convert the AC power panel into a persistent DC power panel. The removable power unit can be mounted in the power panel or can be implemented as a stand-alone external device for connecting to the power panel.

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

Abstract: A semiconductor device includes a first transistor that flows a load current to an external load; a current generation circuit that outputs a current corresponding to a power consumption generated in an overheat detection target when the load current flows the overheat detection target; a resistor-capacitor-network comprising a resistor and a capacitor corresponding to a thermal resistance and a thermal capacitance of the overheat detection target, and having one end coupled to the current generation circuit; an overheat detection circuit coupled to a connection point of the current generation circuit and the resistor-capacitor-network; and a voltage source that sets a voltage of the connection point of the current generation circuit and the resistor-capacitor-network to a predetermined voltage.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: Systems, apparatuses, and methods are described for power conversion. The power conversion may be done by a plurality of power devices with different configurations. For example, the plurality of power devices may include one or more converters with an upside-up buck configuration and one or more converters with an upside-down buck configuration. The power conversion may be done by one or more power devices that may be configurable between different modes of configuration. For example, one or more power converters may be configured in either an upside-up buck configuration mode or an upside-down buck configuration mode. The selection of a certain mode of configuration of the converter may be permanent or non-permanent.

Abstract: The present invention relates to an electronic device, comprising: —a GFET; —noise suppression means comprising: —a modulation unit applying to a gate (G) of the GFET a signal Vg with frequency fm to modulate charge carrier density of a graphene channel around the charge neutrality point between charge carrier density values at frequency fm, —a control unit (CU), and—a demodulation circuit which is CMOS-implemented and that: —comprises first and second circuital branches alternately switchable to demodulate an electrical signal of frequency fm; or—is configured to generate and apply a signal Vb with frequency fmb to a source (S) of the GFET continuously, simultaneously and with a delay td to induce a phase with respect to Vg to yield a maximal demodulated output signal (So). The present invention also concerns to a method for suppressing noise for the device of the invention.

Abstract: A fractional sampling-rate converter includes a first-in first-out (FIFO) buffer, a write logic, a read logic and a fractional interpolator. The write logic is designed to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and is designed to generate corresponding interpolated data samples as an output of the fractional sampling-rate converter at a second rate. The read logic is designed to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator. A ratio of the second rate and the first rate is a fractional number greater than one.

Abstract: A power supply system is operable to harvest power at low and high line currents. A current transformer is arranged to couple to a power transmission line. A current sensor which may be a Rogowski coil is arranged to couple to the power transmission line. Branches of power supply circuitry are connected to a plurality of secondary windings of the current transformer. A control circuit selects one of the branches of power supply circuitry, depending on sensed magnitude of line current, to provide electrical power to an output capacitor. Sufficient stored energy is also provided for performing a backup of operating parameters when the line current reduces to zero.

Abstract: A power detector includes a detection circuit and a bias circuit. The detection circuit is used to receive an input signal and output a power indication signal. The bias circuit includes a first impedance unit, a second impedance unit and a transistor. The transistor includes a first terminal and a control terminal coupled to the first impedance unit, and a second terminal. The second impedance unit is coupled between the first terminal of the transistor and an output terminal of the bias circuit, or between the second terminal of the transistor and a second terminal of the bias circuit. The output terminal of the bias circuit is coupled to an input terminal of the detection circuit, and is used to output a bias signal.

Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: Various embodiments provide for a continuous time linear equalizer (CTLE) that includes an active inductor, which can be included in a receiver portion of a circuit. For some embodiments, the CTLE in combination with the active inductor can implement a signal transfer function comprising at least two zeros and two poles.