Patents Examined by Jon Santamauro
  • Patent number: 6380762
    Abstract: An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. The output buffer is configured to receive the select signal which selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain a constant slew rate while operating in either the first or second state.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: April 30, 2002
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ashish Pancholy, Gary A. Gibbs
  • Patent number: 6340898
    Abstract: An output driver that may be configured to operate as a totem-pole driver, or as an open-drain driver. The output driver comprises a totem-pole driver coupled to an output pin. A control circuit is coupled to the output enable input of the totem-pole driver. The control circuit is supplied with an open-drain control signal controlled by the user interface. When the open-drain control signal is at a first logic level, the output driver operates as an open-drain driver. When the open-drain control signal is at a second logic level, the output driver is configured to operate as a totem-pole driver.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: January 22, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pierre Haubursin, Ching Yu
  • Patent number: 6236228
    Abstract: The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exceed a predetermined value. The inputs and outputs of the standby cells are connected to metal standby tracks being disposed on the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point on the tracks.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: May 22, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Chaisemartin
  • Patent number: 6232793
    Abstract: A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: May 15, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazutami Arimoto, Masaki Tsukude
  • Patent number: 6222391
    Abstract: A circuit for shifting the potential level of an input signal toward higher potentials is added to a conventional differential ECL circuit in order to shift levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials. Thus, the ECL circuit is improved to ensure a continuous flow of a current and to maintain stable operations even at an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around −2 V.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Tadahiro Kuroda
  • Patent number: 6215328
    Abstract: A buffer circuit including a pair of complementary P-channel transistor and N-channel transistor connected in series, the connecting point of which is connected to an output terminal. The gate terminal of the P-channel transistor is connected to a power supply when the input signal is a low level, and to the output terminal when the input signal is a high level. The gate terminal of the N-channel transistor is connected to the output terminal when the input signal is the low level, and to a ground when the input signal is the high level. This makes it possible to solve a problem of a conventional buffer circuit in that an increasing capacity of a load connected to an output terminal increases a delay time between a time the input signal changes to the high level and a time the output signal changes to the high level.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: April 10, 2001
    Assignees: Mitsubishi Electric System LSI Design Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Nasu
  • Patent number: 6208162
    Abstract: A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: March 27, 2001
    Assignee: Altera Corporation
    Inventor: Vincent T. Bocchino
  • Patent number: 6201409
    Abstract: A macrocell for a programmable logic device includes a carry generator for generating a carry input to the macrocell, the carry generator having an inverting input and at least one non-inverting input. A carry decoupler controls the carry generator and allows any macrocell to be decoupled from a next adjacent macrocell. An XOR gate having a first input is coupled to the output of the carry generator and a second input thereof is connected to a logic input to the macrocell. A register is coupled to the output of the XOR gate. A macrocell output selector includes a first input coupled to an output of the register and a second input coupled to the output of the XOR gate.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: March 13, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventors: Christopher W. Jones, Jeffery Mark Marshall
  • Patent number: 6191611
    Abstract: A programmable logic device has logic array blocks (“LABs”) and interconnection resources. For interconnecting signals to, from, and between the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, there is one four-input second-level function block for every four-input first-level function blocks. At least one tri-state buffer is provided in each LAB. Each tri-state buffer may receive a data signal either from one or more function blocks in the associated LAB or from one or more interconnection conductors adjacent to the LAB. The tri-state buffer may buffer one of the received data signals and apply the resulting buffered signal to one or more of the interconnection conductors adjacent to the LAB.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: February 20, 2001
    Assignee: Altera Corporation
    Inventor: K. Risa Altaf
  • Patent number: 6191618
    Abstract: A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Eric Gayles, Bharat Bhushan, Debashree Ghosh
  • Patent number: 6191608
    Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: February 20, 2001
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Srinivas T. Reddy, Kerry Veenstra, Andreas Papaliolios, Chiakang Sung, Richard Shaw Terrill, Rina Raman, Robert Richard Noel Bielby
  • Patent number: 6191616
    Abstract: A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: February 20, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Todd A. Merritt, Troy A. Manning
  • Patent number: 6188338
    Abstract: A coding apparatus and decoding apparatus for easily generating an adaptive Huffman code. A frequency counting element possesses a counter that counts the appearance frequency of a preset dominant symbol candidate included in an input data. A dominant symbol selecting unit selects from a frequency data, data having a larger frequency than a predetermined threshold value and sends the selected data to a code assigning element as a dominant symbol frequency data. A fixed code word memory stores a previously generated Huffman code and sends it to the code assigning element as a fixed code word data. The code assigning element generates a Huffman code for the dominant symbol and synthesizes the Huffman code and the fixed code word data stored in the fixed code word memory to obtain the Huffman code for the whole data. The input data is coded using the Huffman code and an intermediate symbol data. The intermediate symbol data and a Huffman code table data are sent in a coded state.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: February 13, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Taro Yokose
  • Patent number: 6188236
    Abstract: A logic circuit arrangement includes signal input and signal output devices and a number of SFQ circuits having Josephson junctions in which carrier devices are used for carrying digital information. The SFQ circuits are sampled at the input/output for producing DC voltages and a train having at least two single flux quanta is used as a carrier device for information and phase locking between at least two Josephson junctions is used to provide at least two different dynamic states of which at least one provides an output signal.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: February 13, 2001
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Erland Wikborg
  • Patent number: 6184704
    Abstract: This invention describes an improved design of CMOS. digital input circuits. This improvement reduces the switching level uncertainty range and thus increases the noise margin, compensating for manufacturing process variations. This improvement is achieved by providing resistive compensation devices in series with the P-type and the N-type CMOS transistors in the first stage of a multistage digital input circuit. These resistive devices can be implemented by means of resistors or by means of MOSFET devices which provide the required resistive function. These compensation devices modify the input-output voltage transfer characteristics of the first stage so as to reduce the switching level variation at the input to the circuit. The resulting digital input circuit has a greater tolerance to input noise levels. The improvement provided by this invention is particularly important as integrated circuits design trend is to operate with lower supply voltages.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: February 6, 2001
    Assignee: Tritech Microelectronics
    Inventors: Hongwei Wang, Yu David Hu, Chan Chee Oei
  • Patent number: 6184711
    Abstract: A low impact buffer structure disposed in unused silicon area in a signal line routing channel between logic cell rows of an integrated circuit. In a buffer cell according to the invention, power to the buffer is provided by the power supply rails of one or more nearby logic cell rows. Both the connections to the supply rails and the connections between the transistors of the buffer cell are constructed of a polysilicon material and/or lower metal layer. In this manner, the buffer cell does not significantly impact the routing of metal signal lines in the signal line routing channel. In addition, the buffer cells can be arranged in a “staggered” configuration wherein separate buffers are provided in individual routing tracks of a signal line routing channel, further reducing the possibility of interference with normal signal routing.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: February 6, 2001
    Assignee: LSI Logic Corporation
    Inventors: Stefan Graef, Oscar M. Siguenza
  • Patent number: 6184705
    Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: February 6, 2001
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Srinivas T. Reddy, Andreas Papaliolios
  • Patent number: 6184701
    Abstract: Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL, and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: February 6, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-hyun Kim, Ki-whan Song
  • Patent number: 6184702
    Abstract: Offers a circuit that reduces or removes crosstalk with a method that does not exert influence on improvements in miniaturization and the degree of integration. The crosstalk prevention circuit, between at least two signal lines that are formed almost in parallel, for example, a master clock line and a slave clock line 11, 12, makes a third signal line 13 that applies a signal when a signal is not applied to at least one of these two signal lines, for example, a test signal, and becomes in a grounded condition when a signal is applied to the above-mentioned two signal lines. Preferably, a driver circuit is connected to the third signal line, and the ratio of the current drive capabilities of the N channel transistor and the P channel transistor of the output transistors of said driver circuit is made about 2:1.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: February 6, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Takahashi, Kayoko Ozawa, Kenichi Tashiro
  • Patent number: 6184710
    Abstract: A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: February 6, 2001
    Assignee: Altera Corporation
    Inventor: David W. Mendel