Abstract: A circuit that provides a termination resistance to a transmission line includes a controllable termination resistor coupled between the transmission line and a termination voltage node. The circuit also includes a control circuit coupled to the controllable termination resistor and to a reference resistor. The control circuit matches the resistance of the controllable termination resistor to the resistance of the reference resistor.

Abstract: There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage coupled to the buffer input node. The input stage is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage coupled to the input stage. The level shifter stage is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage coupled to the level shifter stage.

Abstract: A structure for providing clearing/programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops. One method for clearing and programming a programmable logic device includes arranging a plurality of memory cells in sets, clearing the sets in a first spatial sequence, and programming the sets in a second spatial sequence. Sets of memory cells could include columns of memory cells, each column having an associated storage element. In this manner, a plurality of columns of memory cells can be cleared or programmed in any predetermined order.

Abstract: In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic has been employed to work around the problems caused by the defective device. Higher device speeds and increasingly complex bus protocols have made the technique of singly using programmable logic, more difficult to implement. The addition of bidirectional switches integrated with and controlled by programmable logic in a monolithic integrated circuit allows the programmable logic device to respond more quickly while at the same time consuming less printed circuit board space. Additionally, the invention provides for termination of the isolated device and/or signal line stubs.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: A domino logic circuit having output noise elimination is disclosed. A compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.

Abstract: A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.

Abstract: A wordline decoder circuit and method of decoding a wordline input signal are provided. A first decoder receives multiple inputs to be evaluated. The first decoder includes a first precharge device for precharging a first node and a first discharge device to enable discharging the first node. A first clock signal enables the first discharge device. The first clock signal disables the precharge device. A clock delay circuit receives the first clock signal and generates a delayed clock signal. A second logic is coupled to the first decoder. The second logic provides a wordline output. The second logic wordline output is enabled responsive to the delayed clock signal and is disabled responsive to the first clock signal.

Abstract: The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions.

Abstract: An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

Abstract: Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.

Abstract: An electronic system includes a plurality of electronic circuits each having a signal input and output function, a bus to which the plurality of electronic circuits are connected, first termination resistors connected to ends of the bus, and a termination voltage circuit having a first part generating a first voltage and a second part generating a second voltage. The sum of the first voltage and the second voltage is supplied, as a power supply voltage, to output circuits of the plurality of electronic circuits connected to the bus. The second voltage is supplied to the first termination resistors as a termination voltage.

Abstract: Integrated circuits include an impedance control circuit having at least one output terminal coupled to an on-chip reference termination device in order to control output impedance of the reference termination device such that it matches that of an external resistance. The impedance control circuit outputs are also coupled to the on-chip impedance-controlled termination devices which are coupled to each of the external transmission lines to be terminated. In this way, a single reference resistance allows many transmission lines to be properly terminated. The impedance-controlled termination devices are may be implemented as pairs of binary weighted p-channel and n-channel field effect transistors.

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.

Abstract: A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

Abstract: A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication processes has a precharge transistor connected between a precharge volt source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value.

Abstract: An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.