Abstract: A method for making a semiconductor device includes:a step for preparing a substrate;a step for forming a wiring layer on the substrate;a step for loading the substrate onto a substrate supporting unit in a reaction chamber;a step for supplying a material gas essentially consisting of a silane gas, an oxidizing gas and a chalcogen fluoride gas into the reaction chamber; anda step for forming a silicon oxide insulating film containing fluorine on the substrate by a plasma CVD process.

Abstract: A semiconductor device fabrication process in which an oxynitride layer and a polysilicon layer are formed in the same reaction chamber is provided. In accordance with one embodiment of the invention, a semiconductor device is formed by forming, in a reaction chamber, an oxynitride layer on a surface of a substrate and forming, in the same reaction chamber, a polysilicon layer over the oxynitride layer. The oxynitride layer may be used to form a gate oxide and the polysilicon layer used to form a gate electrode.

Abstract: A method of manufacturing an inverse-staggered self-aligned thin film transistor on a substrate having a front surface and a back surface is provided. The method includes the steps of (a) forming a gate electrode over the front surface of the substrate,(b) forming a gate insulating layer over the gate electrode,(c) forming a semiconductor active layer over the gate insulating layer adjacent the gate electrode. The method further includes the steps of (d) forming an impurity-doped semiconductor layer over the active layer and (e) radiating a laser beam from the back side of the substrate using the gate electrode as a mask to substantially crystallize portions of the active layer and the impurity-doped semiconductor layer to define source and drain regions in the active layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of field oxide layers on a semiconductor substrate to define an active region; forming a plurality of gate electrodes each having sidewall spacers on the active region of the semiconductor substrate, depositing a metal layer on the semiconductor substrate including the plurality of gate electrodes, defining a first region and a second region, removing the metal layer over the second region, and forming a silicide layer on the gate electrode and on the semiconductor substrate over the first region with a first annealing process.

Abstract: A semiconductor device fabricating method is capable of securing an increased margin for absorbing an error in aligning a viahole with an underlying wiring layer when forming a viahole in a layer insulating film to connect an upper wiring layer overlying the layer insulating film and a lower wiring layer underlying the layer insulating film to enable the miniaturization of a pattern and the miniaturization of the semiconductor device. The semiconductor device fabricating method forms a first Si.sub.3 N.sub.4 film between a first wiring layer and a second wiring layer, and a second layer insulating film, a third layer insulating film and a fourth layer insulating film all of SiO.sub.2 over the second wiring layer. When forming a third viahole through the layer insulating films so as to reach the second wiring layer, the layer insulating films are etched in a high SiO.sub.2 /Si.sub.3 N.sub.4 selectivity of about twenty.

Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

Abstract: The specification describes methods for making T-shaped metal gates for Schottky gate devices such as MESFETs and HEMTs. The method uses a bi-level photoresist technique to create a T-shaped feature for the gate structure. The metal gate is evaporated into the photoresist T-shaped feature and a lift-off process is used to remove unwanted metal. The photoresist is the dissolved away leaving the T-shaped gate. An important aspect of the process is the use of a plasma treatment of the first patterned resist level to harden it so that it is unaffected by the subsequent deposition and patterning of the second level resist.

Abstract: An insulating film is formed by CVD on the surface of a semiconductor substrate formed with circuit elements such as transistors, and thereafter a hydrogen silsesquioxane resin film is formed on the insulating film by spin-coating or the like. This resin film is sequentially subjected to low temperature annealing at 400.degree. C. or lower and then to high temperature annealing at 700.degree. C. or higher. The low temperature annealing changes the resin film into a silicon oxide film, and the high temperature annealing is performed in order to make dense the film quality of the silicon oxide film. The high temperature annealing is performed by rapid thermal annealing in an oxidizing atmosphere of water vapor or the like. A CVD insulating film is formed on the densified silicon oxide film and planarized by CMP or the like, according to necessity. A contact hole is formed through the CVD insulating film, densified silicon oxide film and the insulating film, and a wiring layer is thereafter deposited.

Abstract: A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions.In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

Abstract: Anodising treatments are used to form insulating films (12) in the manufacture of a flat-panel display or other large-area thin-film electronic device. A first film (1,101) of anodisable material (e.g Al) is anodised through a part of its thickness to form an anodic second film (2). A mask pattern (4), e.g of photoresist, is provided at least on the second film (2) to define an area (5) where the second film (2) is etched away through at least a part of its thickness and where a further anodising step is carried out to form an anodic third film (3) contiguous with a remaining part of the anodic second film (2). The manufacture is simplified by using reverse-anodising in an electrolyte solution (20) to carry out the etching of the second film (2).

Abstract: A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first and second channel regions each having a different concentration level, a gate insulating film having a step difference, a gate electrode having a step difference, a drain region including first, second, and third impurity regions, a source region including first and third impurity regions, a spacer, an interlayer dielectric film and a metal electrode. Threshold voltage can be maintained to an appropriate level, junction break voltage can be increased, and the punchthrough characteristic can also be enhanced.

Abstract: The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. The removal or detachment of an electron source from the semiconductor substrate eliminates the heavily-doped source drain diffusion or implant into a source region of the substrate, thereby avoiding non-uniform doping profiles that degrade long-channel subthreshold characteristics of a device as well as the punchthrough behavior of short-channel devices. A metal plug is used as an electron source which is removed or detached from the from the semiconductor substrate. The metal plug is vastly superior to doped semiconductor materials as an electron source. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping.

Abstract: A method of manufacturing a vacuum device utilizing a sputtering process is disclosed. According to the present invention, the vacuum device includes a silicon substrate. An emission electrode having a sharp ended tip is formed by etching the silicon substrate. An insulating layer is formed on the silicon substrate so as to make the entire structure of the emission electrode to be exposed, with the emission electrode being surrounded by the insulating layer. A gate electrode is then formed adjacent to the sharp ended tip of the emission electrode. According to the present invention, it has advantages that the emission electrode is manufactured by forming the silicon pillar using the isotropic etching and anisotropic etching and the gate electrode can be easily formed adjacent to the emission electrode by using the sputtering method after the gate insulating layer is formed.

Abstract: After forming an isolation layer and a well region on and in a silicon substrate, a gate oxide layer, a gate electrode of polycrystalline silicon and an oxide layer on the gate electrode are formed. Subsequently, a side wall of a nitride layer is formed. Then, the oxide layer on the gate electrode is removed. Next, selective growth of impurity doped silicon is performed at a temperature lower than or equal to 800.degree. C. to form an elevated source-drain region in a source-drain region. Also, a polycrystalline silicon layer is formed on the gate electrode. Thereafter, by performing heat treatment, the impurity is diffused from the source-drain region to the surface of the silicon substrate to form a source-drain diffusion layer. Simultaneously, conductivity is provided to the entire gate electrode by diffusing impurity from the polycrystalline silicon layer to the gate electrode.

Abstract: Methods of depositing films on semiconductor wafers include the steps of loading a deposition apparatus with a first plurality of semiconductor wafers from a first run cassette and then depositing a first material such as undoped silica glass (USG) or borophosphosilicate glass (BSPG), for example, thereon. After a first film has been completely deposited on each of the loaded wafers, a first wafer in the first plurality is removed from the apparatus and another wafer from the first run cassette is loaded into the apparatus. A second film of the first material is then deposited on the remaining first plurality of wafers and the added wafer. Following this deposition step, a second wafer from the first plurality is removed from the apparatus and another wafer (e.g., seventh wafer) from the first run cassette is loaded into the apparatus.

Abstract: A semiconductor processing method for forming a diffusion region is described and which includes providing a semiconductor substrate; forming a first layer of material over the semiconductor substrate; and after forming the first layer, ion implanting a conductivity modifying impurity through the first layer and into the semiconductor substrate to form a diffusion region therein. In an alternative form, a method for forming a field effect transistor is described and which includes providing a substrate; forming a field oxide region and active area region on the substrate; forming a gate dielectric layer atop the substrate and within the active area region; and after forming the gate dielectric layer, ion implanting a dopant impurity through the field oxide region and into the underlying substrate to form a field implant beneath the field oxide region for facilitating electrical isolation of the field effect transistor from adjacent electrical devices.

Abstract: For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.