Abstract: A capacitor for high density DRAM applications comprises a high-.epsilon. capacitor dielectric such as BST or PZT in an arrangement which obviates the need for barrier layers during fabrication. The fabrication process allows for electrode placement by simple sputter deposition and further provides for the possibility of capacitor spacing below that of conventional lithographic techniques.

Abstract: A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in electron or hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.

Abstract: A second insulating layer is used to mask a first insulating layer on a second gate electrode, during fabrication of a conductive contact adjacent a first gate electrode which is spaced apart from the second gate electrode. By using the second insulating layer as a sacrificial insulating layer during etching of the conductive contact, thinning of the first insulating layer on the second gate electrode may be prevented. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit surface. The first and second spaced apart gate electrodes include first and second sidewalls, respectively. The first insulating layer and the second insulating layer are formed on the integrated circuit surface, including on the first and second gate electrodes. The second insulating layer is removed from the first gate. The first insulating layer is etched on the first gate to thereby form first spacers on the first sidewalls.

Abstract: The invention relates to integrated circuits and to methods of forming self-aligned silicidation structures. In an exemplary embodiment, a first insulating layer is formed on the surface of a semiconductor substrate which includes an electrode. A second insulating layer is formed over the first insulating layer and a photoresist pattern is formed over a silicide exclusion area. Exposed portions of the first and second insulating layers are removed by one or more etching steps, wherein an etchant used to remove the exposed portions of the second insulating layer has a higher selectivity for the second insulating layer than for the first insulating layer. A silicide layer can then be formed over the surface of the semiconductor substrate except for silicide exclusion areas. Modification of the profiles of features underlying the first insulating layer, such as sidewall spacer and field oxides can thereby be prevented.

Abstract: A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.

Abstract: Methods of forming DRAM memory devices include the steps of forming deep storage electrode contact regions to improve the refresh characteristics of DRAM memory cells therein. In particular, the methods include the steps of forming an array of DRAM memory cells in a field ion region of second conductivity type. These memory cells contain storage electrode contact regions and bit line contact regions of first conductivity type therein. An electrically insulating layer is then deposited on the memory cells. Storage electrode contact holes are formed in the electrically insulating layer to expose the storage electrode contact regions. Dopants of first conductivity type are then implanted through the storage electrode contact holes and into the storage electrode contact regions at a first energy in a range between about 60 and 150 KeV. Then, dopants of first conductivity type are again implanted through the storage electrode contact holes at a second higher energy in a range between about 200 and 450 KeV.

Abstract: A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.

Abstract: The preferred embodiment provides a method for fabricating field effect transistors that have different threshold voltages without requiring excessive masking and other fabrication steps. In particular, the method facilitates the formation of FETs with different threshold voltages by doping the gate dielectric with various amounts of ions. This provides a built in potential in the gate dielectric proportional to the amount of ions in the gate dielectric. This potential changes the threshold voltage of the FET. Thus, by selectively doping the gate dielectric with ions the threshold voltage of a FET can be changed. The selective doping of many FETs to many different threshold voltages can be done with only one additional masking step. Thus, the present invention provides the ability to form FETs having different threshold voltages without requiring excessive process complexity.

Abstract: A method for forming a gate with a tapered spacer is disclosed. The method includes forming a polysilicon layer on a substrate, and then forming a first oxide layer on the polysilicon layer. A photoresist layer is formed on the first oxide layer, where the photoresist layer defines a gate region, and then portions of the oxide layer and the polysilicon layer are removed using the photoresist layer as a mask, thereby forming a gate. A second oxide layer is formed on the substrate and the first oxide layer. Afterwards, the second oxide layer is isotropically etched so that the slope of the second oxide layer near the upper corners of the gate is reduced. Finally, the second oxide layer is anisotropically etched back to form spacers on the sidewalls of the gate.

Abstract: A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface.

Abstract: An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed.