Patents Examined by Jonathan R Labud
  • Patent number: 8656355
    Abstract: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 18, 2014
    Assignee: CA, Inc.
    Inventors: Steven M. Oberlin, David W. McAllister
  • Patent number: 8635594
    Abstract: Described are techniques for configuring a target data store. Code written in a scripting language is provided. The scripting language includes environment blocks that retrieve data used in a subsequent block and execution blocks that execute an operation to configure said target data store. The retrieved data includes data from said target data store. The code is processed and includes retrieving data in accordance with environment blocks included in the code, and updating said target data store in accordance with execution blocks included in said code.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 21, 2014
    Assignee: EMC Corporation
    Inventors: Sriram Krishnan, Russell R. Laporte
  • Patent number: 8627268
    Abstract: A system and method for a non-sequential undo mechanism is presented. An action removal manager stores program states and action descriptions that it receives from a user in a program log corresponding to a software application. In turn, the action removal manager allows the user to remove an action from the program log without first removing actions subsequent to the action that, as a result, undoes an action to a file without undoing subsequent actions to the file. In one embodiment, the undo request includes a request to remove two or more actions from the program log. In this embodiment, the action removal manager evaluates the earliest action description to remove in the program log and then proceeds to evaluate subsequent action descriptions for removal.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Robert Edward Lee
  • Patent number: 8615758
    Abstract: A self-replicating machine includes a virtualization tool, a provisioning tool, and a configuration tool, stored in a distributable self-contained repository of the machine. The machine is able to automatically rebuild itself solely from the tools stored in the distributable self-contained repository. The virtualization tool is configured to build one or more virtual machines on the machine. Each virtual machine has a corresponding operating system and environment. The provisioning tool is configured to provision the one or more virtual machines. The configuration tool is to configure the one or more provisioned virtual machines. A custom configuration management tool further customize and configure the physical machine for specific users. A source code management tool stored in the distributable self-contained repository is configured to develop each virtual machine independently from each other in parallel, and to merge back the developments to a corresponding parent virtual machine.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: December 24, 2013
    Assignee: Red Hat, Inc.
    Inventors: Matt Hicks, Brenton Leanhardt, Christopher Alfonso, Chris MacLeod
  • Patent number: 8607236
    Abstract: An information processing system is provided to alleviate excessive load on a master node, thereby allowing the master node to efficiently perform the process of assigning jobs to nodes. A client 10 classifies a plurality of jobs constituting a large-scale arithmetic operation into several blocks, and requests a master node 20 to process the jobs block by block, such that the master node 20 always performs the process of assigning a predetermined number of jobs or less. Here, the predetermined number is preferably determined in such a manner as to allow the master node 20 to efficiently perform the process of assigning the jobs to nodes, even if the number of nodes is significant. As such, the client 10 has the function of controlling the load on the master node 20, and therefore it is possible to prevent the load on the master node 20 from increasing.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: December 10, 2013
    Assignee: NS Solutions Corporation
    Inventors: Shinjiro Kawano, Makoto Tensha, Katsumi Shiraishi
  • Patent number: 8578388
    Abstract: A hybrid CPU system wherein the plurality of processors forming the hybrid system are initially undifferentiated by type or class. Responsive to the sampling of the threads of a received and loaded computer application to be executed, the function of at least one of the processors is changed so that the threads of the sampled application may be most effectively processed/run on the hybrid system.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Diane Flemming, Greg R. Mewhinney, David B. Whitworth, Randal C. Swanberg, Eric P. Fried
  • Patent number: 8572560
    Abstract: Collaborative program development systems are provided which implement methods for providing automated programming assistance to code developers in a collaborative program development environment. In particular, systems and methods for automated programming assistance are supported by leveraging a database or library of shared code snippets that are classified according to code patterns and rating scores that are derived from feedback and input from various code developers within a collaborative program development environment.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Youssef Drissi, Daby M. Sow
  • Patent number: 8572631
    Abstract: Systems and methods are provided for controlling a device. In one aspect, a method for controlling a device includes exposing a plurality of virtual device interfaces (13) for a device (11), wherein each virtual device interface (13) enables client control of a discrete function of the device, and controlling concurrent communication between the device (11) and two or more virtual device interfaces (13) operating on a single shared I/O connection (15) using a shared I/O port controlled by a device I/O module (12). The device I/O module (12) enables independent development of multiple device interfaces (13) that can seamlessly and independently operate on a single (physical) device communication connection (15), wherein the device shared I/O (input/output) module (12) implements functions to arbitrate and coordinate I/O activity between the device interfaces (13) and target device (11).
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 29, 2013
    Assignee: GVBB Holdings S.A.R.L.
    Inventor: Gerald Philip Wilson
  • Patent number: 8566791
    Abstract: The present invention provides an inexpensive, software-based security-retrofit solution to verify the integrity of program code in embedded systems, or accessories, without resorting to expensive hardware changes. All unused memory on an accessory that could be used to store a program code image is filled with random data. A host system also locally stores a copy of the accessory's program image containing the random data. The host system sends the accessory a list of memory addresses or memory ranges on the accessory, which is always different and random in nature. The accessory will then produce a digest using values stored in the memory addresses as inputs to a secure hash function. The host system verifies the integrity of the embedded program code by verifying the resulting digest produced by and returned from the accessory.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: October 22, 2013
    Assignee: BlackBerry Limited
    Inventors: Ashok Vadekar, Brian Neill
  • Patent number: 8549524
    Abstract: In a computer system with a multi-core processor, the execution of tasks is scheduled in that a first queue for new tasks and a second queue for suspended tasks are related to a first core, and a third queue for new tasks and a fourth queue for suspended tasks are related to a second core. The tasks have instructions, the new tasks are tasks where none of the instructions have been executed by any of the cores, and the suspended tasks are tasks where at least one of the instructions has been executed by any of the cores. New tasks are popped from the first queue to the first core; and in case the first queue being empty, tasks are popped to the first queue in the following preferential order: suspended tasks from the second queue, new task from the third queue, and new tasks from the fourth queue.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 1, 2013
    Assignee: SAP AG
    Inventor: Alin N. Jula
  • Patent number: 8533680
    Abstract: A finite domain approximation for symbolic terms of a symbolic state is derived, given some finite domains for basic terms of the symbolic state. A method is executed recursively for symbolic sub-terms of a symbolic term, providing a domain over-approximation that can then be provided to a solver for determining a more accurate domain. The method can be applied to a wide array of system terms, including, for example, object states, arrays, and runtime types.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: September 10, 2013
    Assignee: Microsoft Corporation
    Inventors: Nikolai Tillmann, Wolfgang Grieskamp, Wolfram Schulte
  • Patent number: 8522242
    Abstract: A batch computer or batch processor may implement conditional execution at the command level of the batch processor or higher. Conditional execution may involve execution of one batch buffer depending on the results achieved upon execution by another batch buffer.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Hong Jiang, Wishwesh Gandhi
  • Patent number: 8516494
    Abstract: Methods, apparatus, and products are disclosed for executing an application on a parallel computer that include: executing, by a current compute node, a current task of the application, including producing results; determining, by the current compute node in dependence upon current network characteristics and application characteristics, whether to transfer the results to a next compute node for further processing by a next task on the next compute node or to execute the next task for further processing of the results on the current compute node; transferring, by the current compute node, the results to the next compute node for further processing by the next task on the next compute node if the determination specifies transferring the results to the next node; and executing, by the current compute node, the next task for further processing of the results if the determination specifies executing the next task on the current compute node.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Michael B. Brutman, David L. Darrington, Amanda E. Peters, John M. Santousso
  • Patent number: 8516499
    Abstract: Assistance in performing an action for a detected event for a monitoring target resource whose connection is not an always-on connection to perform an appropriate action as soon as possible in response to occurrence of a failure. The assistance device stores, in association with an occurrence pattern of an event, information related to plural tasks for determining whether a predetermined condition is fulfilled, and an action to be performed by a corresponding device. Then, the assistance device calculates an index value for determining the level of probability of the occurrence pattern of the event, determines whether the calculated index value is larger than a predetermined value, and sends, to a device to perform the action, the occurrence pattern of the event the index value of which is determined to be larger than the predetermined value, and information related to the plural tasks and the action corresponding to the occurrence pattern.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kazuhito Akiyama, Yasutaka Nishimura, Tadashi Tsumura
  • Patent number: 8516491
    Abstract: An algorithm in a multi-core processor having a plurality of cores for deciding processing allocation to each core to distribute the processing load thereof, and an efficient processing allocation algorithm simplified for software engineers are established. In order to achieve the above processing load distribution, the multi-core processor includes a plurality of basic modules divided into minimum configuration units, each having a uniform input/output format interface, so as to perform required processing contents in the overall processor. As an initial allocation, the above plurality of basic modules are allocated in distribution to the above plurality of cores, and subsequently, based on functional information of each core, the above plurality of initially allocated basic modules are relocated either periodically or at appropriate timing.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Limited
    Inventors: Daisuke Nitta, Tomonori Kumagai, Kazunari Kobayashi
  • Patent number: 8516444
    Abstract: Methods, apparatus, and computer program products are disclosed for debugging a high performance computing program by gathering lists of addresses of calling instructions for a plurality of threads of execution of the program, assigning the threads to groups in dependence upon the addresses, and displaying the groups to identify defective threads.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventor: Thomas M. Gooding
  • Patent number: 8499296
    Abstract: A system for managing updates of an executable component in accordance with an updating tree with multiple branches is provided. In one implementation, specific updates are provided to users with specific problems while general updates are provided to all users of the executable component. A range of lower version numbers is reserved for the general updates. When a specific update with a version number higher than those in the reserved range has been installed on a computing device, an installer may prevent a new general update with a lower version number to be installed. The installer may determine a new specific update corresponding to the general update and provide an indication to the user to install this new specific update instead of the general update. This multi-branch update delivery system enables users to elect to receive only updates that are necessary.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: July 30, 2013
    Assignee: Microsoft Corporation
    Inventors: Scott A. Konersmann, Arulkumar Elumalai, Maxwell D. Myrick
  • Patent number: 8495578
    Abstract: The invention relates to an integrated software development system 4, comprising an interface description language adapted to specify constraints on input parameters, a program analyzer 6 adapted to identify input parameters of a software program 7, and a validation enforcement system 5 adapted to enforce that an interface description 8 in the interface description language complying with a predefined set of validation rules 9 is provided for the input parameters of the software program 7. The invention further relates to a method for validation, a computer arrangement and a computer program product.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventor: Philippe A. Janson
  • Patent number: 8484620
    Abstract: A method, apparatus and computer program product are provided for implementing performance impact reduction of watched variables. Source code is parsed and a variable in the source code to be watched is identified. The identified variable is allocated to a predefined page of storage. The predefined page of storage is separated from frequently accessed variables, such as, a page containing least frequently modified variables, a last page associated with a static storage, and a separate page added for receiving the identified variables to be watched.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Cary Lee Bates, John Matthew Santosuosso
  • Patent number: 8473948
    Abstract: One embodiment of the present invention sets forth a technique for synchronizing the execution of multiple cooperative thread arrays (CTAs) implementing a parallel algorithm that is mapped onto a graphics processing unit. An array of semaphores provides synchronization status to each CTA, while one designated thread within each CTA provides updated status for the CTA. The designated thread within each participating CTA reports completion of a given computational phase by updating a current semaphore within the array of semaphores. The designated thread then polls the status of the current semaphore until all participating CTAs have reported completion of the current computational phase. After each CTA has completed the current computational phase, all participating CTAs may proceed to the next computational phase.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: June 25, 2013
    Assignee: NVIDIA Corporation
    Inventor: Scott M. Le Grand