Patents Examined by Joni Y. Chang
  • Patent number: 5407487
    Abstract: A method and apparatus for producing a nickel shell mold by nickel vapour deposition onto a mandrel in a deposition chamber is disclosed. A nickel shell mold assembly is produced having a liquid and vapour-tight cavity co-extensive with the mandrel for receiving a heating fluid, preferably a liquid such as oil, for flood heating of the mandrel to a uniform surface temperature.
    Type: Grant
    Filed: May 5, 1994
    Date of Patent: April 18, 1995
    Assignee: Weber Manufacturing Limited
    Inventors: Reinhart Weber, Robert Sheppard
  • Patent number: 5405480
    Abstract: An induction plasma source for integrated circuit fabrication includes a hemispherically shaped induction coil in an expanding spiral pattern about the vacuum chamber containing a semiconductor wafer supported by a platen. The windings of the induction coil follow the contour of a hemispherically shaped quartz bell jar, which holds the vacuum. The power source is a low frequency rf source having a frequency of about 450 KHz and a power in the range of 200-2000 watts, and the pressure is a low pressure of about 0.1-100 mTorr. A high frequency rf source independently adjusts the bias voltage on the wafer.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: April 11, 1995
    Assignee: Novellus Systems, Inc.
    Inventors: Jeffrey C. Benzing, Eliot K. Broadbent, J. Kirkwood H. Rough
  • Patent number: 5405488
    Abstract: A plasma etching endpoint detection system monitors two optical wavelengths during etching of a non-opaque dielectric film. A controller coupled to the optical monitoring equipment generates an endpoint detection signal corresponding to a predefined mathematical combination of the monitored intensity of light at the first wavelength and the monitored intensity of light at the second wavelength. When the endpoint detection signal crosses a threshold level, the etching of the dielectric layer is stopped. In a preferred embodiment the two monitored wavelengths differ by approximately a factor of two. More generally, the two monitored wavelengths are selected such that the combined intensity signal has a proportionally smaller false endpoint peak than either of the individual monitored intensity signals.
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: April 11, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Dimitrios Dimitrelis, Calvin T. Gabriel, Samuel V. Dunton
  • Patent number: 5403400
    Abstract: The heat sink is mounted on a semiconductor chip module sealed hermetically with a cap. The heat sink comprises an absorption means for absorbing the heat generated from a semiconductor chip, being inserted into an opening formed in a cap so as to make contact with a semiconductor chip sealed hermetically within a semiconductor chip module; a heat dissipation means exposed outside the cap for dissipating the heat of the semiconductor chip absorbed by the absorption means; and a contact surface disposed between the absorption means and the heat dissipation means and fixed on the upper surface of the cap, and the contact surface at least being coated with an adhesive material. The heat sink mounted on a semiconductor chip module can stably dissipate the heat produced from a semiconductor chip sealed hermetically within the semiconductor chip module.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: April 4, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5399230
    Abstract: A compound semiconductor is etched by a step of substituting a composite element of a compound semiconductor with other element, thereby forming a compound layer on the surface of the compound semiconductor and a step of removing the compound layer from the surface. Etching depth is controlled not by etching time, but by the number of runs (repetitions) of the etching step, and thus can be precisely controlled.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: March 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Takatani, Takeshi Kikawa, Chushirou Kusano, Masatoshi Nakazawa
  • Patent number: 5399529
    Abstract: Disclosed is a process for producing semiconductor devices of multilevel interconnection structure which are absolutely free from cracking in the insulator films and voids or disconnections in the aluminum wirings. After a fluorine-containing silicon oxide film 4 is formed at a temperature of 50.degree. C. or less using an alkoxyfluorosilane vapor and a water vapor, a spin-on glass film 5 is formed thereon by baking at a temperature of 200.degree. C. or less, which is exposed to the alkoxyfluorosilane vapor to effect condensation of the spin-on glass film at room temperature, and then an insulator film is formed thereon, using the thus treated spin-on glass film as a flattening material.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: March 21, 1995
    Assignee: NEC Corporation
    Inventor: Tetsuya Homma
  • Patent number: 5397429
    Abstract: A high frequency, high voltage spark generator is used to create a large number of sparks to erode the surface of a silicon wafer to a depth of up to 100 microns. After a sufficient amount of erosion has occurred, but prior to any macro-scale removal of material, the surface layer of the silicon wafer becomes porous and photoluminescing. The method can be performed in ambient atmosphere and temperature, or in specific gas atmospheres and at different temperatures. The method produces photoluminescing porous silicon layers on p-type, n-type, low-doped, high-doped or undoped silicon wafers.
    Type: Grant
    Filed: September 14, 1993
    Date of Patent: March 14, 1995
    Assignee: University of Florida
    Inventors: Rolf E. Hummel, Sung-Sik Chang
  • Patent number: 5395474
    Abstract: A semiconductor wafer etching apparatus is capable of anisotropically etching a large-diameter semiconductor wafer with high accuracy without causing the semiconductor wafer to be charged. First, the apparatus cools the wafer in an atmosphere of a nitrogen or a halogen gas so that the wafer adsorbs and is covered by atoms of the gas. Then, a fast atom beam source of the apparatus generates an electrically neutral fast atom beam of gas atoms or molecules to etch the semiconductor wafer. The etching speed is promoted by an interaction of the adsorbed atoms and the fast atom beam.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: March 7, 1995
    Assignee: Ebara Corporation
    Inventors: Hidenao Suzuki, Tatsuya Nishimura, Yoshio Hatada
  • Patent number: 5391252
    Abstract: A plasma assembly including an RF head extending into a vacuum chamber and an associated electrode for generating a confined plasma. The assembly includes a sidewall within the chamber forming a plenum about the RF head. The plenum defines a volume substantially smaller than the volume of the chamber and hence, the gas pressure within the plenum is more easily monitored and controlled by the provision of make-up gas.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: February 21, 1995
    Assignee: Hughes Aircraft Company
    Inventor: William D. Taylor
  • Patent number: 5385636
    Abstract: A metal contact is formed by etching a metal film that is locally protected by a spot of photosensitive resin. Thereafter the resin is caused to flow in the presence of vapor of a solvent for the resin, so as to form a protective spot of increased size. This larger spot makes it possible to etch the semiconductor substrate while ensuring that the projection formed in this way is automatically aligned relative to the metal contact. The resin remains photosensitive, thereby enabling subsequent etching. The invention is particularly applicable to the manufacture of avalanche diodes.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: January 31, 1995
    Assignee: Alcatel N.V.
    Inventors: Francis Poingt, Elisabeth Gaumont-Goarin, Lionel Le Gouezigou
  • Patent number: 5376216
    Abstract: A plurality of substrate holding members and a substrate pressing member are disposed on a rotation stage at a peripheral portion. The substrate pressing member includes a magnet and is pivotally supported by the rotation stage. A ring-shaped permanent magnet is located below the rotation stage and forms a ring around the rotation axis of the rotation stage. When a substrate mounted on the rotation stage is rotated and processed, the ring-shaped permanent magnet is positioned in the vicinity of the magnet of the substrate pressing member. This creates a magnetic force between the magnets, causing the substrate pressing member to pivot so that the substrate pressing member contacts the edge of the substrate with a predetermined amount of pressure.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: December 27, 1994
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Katsushi Yoshioka, Koji Nakagawa, Masayuki Itaba, Nobuyasu Hiraoka, Masafumi Takeoka
  • Patent number: 5376593
    Abstract: A method for fabricating semiconductor wafers is disclosed, wherein a semiconductor substrate is provided in a chamber. Subsequently, a first silicon nitride layer is formed in situ under high pressure superjacent the substrate by introducing a gas containing nitrogen, preferably NH.sub.3 combined with N.sub.2, at a temperature within the range of 850.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds. This results in the first layer having a thickness in the approximate range of 5 .ANG. to 30 .ANG.. A semiconductor film is then deposited in situ under high pressure superjacent the first silicon nitride layer, preferably by means of Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"). In an alternate embodiment of the present invention, this is accomplished by either Low Pressure Chemical Vapor Deposition ("LPCVD") or Molecular Beam Epitaxy ("MBE"). The thickness of the film is in the approximate range of 10 .ANG. to 40 .ANG..
    Type: Grant
    Filed: December 31, 1992
    Date of Patent: December 27, 1994
    Assignee: Micron Semiconductor, Inc.
    Inventors: Gurtej S. Sandhu, Randhir P. S. Thakur
  • Patent number: 5376213
    Abstract: A plasma etching apparatus includes a wafer-mount arranged in an aluminum-made process chamber. The wafer-mount comprises an aluminum-made susceptor, a heater fixing frame and a cooling block, and a ceramics heater is attached to the heater fixing frame. A bore in which liquid nitrogen is contained is formed in the cooling block. The cold of the cooling block is transmitted to a wafer on the susceptor to cool it while it is being etched. The ceramics heater adjusts the temperature of the wafer cooled. Liquid nitrogen is circulated in the bore in the cooling block, passing through coolant passages defined by a pair of joint devices which connect the bottom of the process chamber and the cooling block to each other.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: December 27, 1994
    Assignee: Tokyo Electron Limited
    Inventors: Yoichi Ueda, Mitsuaki Komino, Koichi Kazama
  • Patent number: 5362353
    Abstract: An improved Faraday Cage is provided for use in reducing ion damage to semiconductor wafers during plasma etching. The improved Faraday Cage consists of a cylindrical metallic chamber having a cap at one or more ends. Semiconductor wafers are placed within the Cage and the Cage is suitably disposed within a plasma etcher. The caps substantially reduce the amount of harmful radiation which can enter the Cage and thereby ion damage to the wafers contained therein. The improved Faraday Cage can be conveniently integrated with a barrel-style plasma etcher by securing one of the Cage caps to the door of the plasma etcher such that opening and closing the door serves to disengage and engage one of the caps from the Cage.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: November 8, 1994
    Assignee: LSI Logic Corporation
    Inventor: Thomas G. Mallon
  • Patent number: 5358901
    Abstract: The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: October 25, 1994
    Assignee: Motorola, Inc.
    Inventors: Robert W. Fiordalice, Stanley M. Filipiak, Johnson O. Olowolafe, Hisao Kawasaki
  • Patent number: 5346578
    Abstract: An induction plasma source for integrated circuit fabrication includes a hemispherically shaped induction coil in an expanding spiral pattern about the vacuum chamber containing a semiconductor wafer supported by a platen. The windings of the induction coil follow the contour of a hemispherically shaped quartz bell jar, which holds the vacuum. The power source is a low frequency rf source having a frequency of about 450 KHz and a power in the range of 200-2000 watts, and the pressure is a low pressure of about 0.1-100 mTorr. A high frequency rf source independently adjusts the bias voltage on the wafer.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: September 13, 1994
    Assignee: Novellus Systems, Inc.
    Inventors: Jeffrey C. Benzing, Eliot K. Broadbent, Kirkwood H. Rough