Abstract: A method of electron cyclotron resonance plasma etching including generating a constant plasma in a gas in a chamber containing a semiconductor wafer by supplying microwave energy to the chamber continuously and applying a pulsed direct current bias to the semiconductor wafer, wherein the pulsed bias has a period substantially equal to a time constant determined by the capacitance of the semiconductor wafer and the resistance of an ion sheath at the surface of the semiconductor wafer.

Abstract: A gas injection system employs a crucible having a plurality of cylindrical bores within which gas is generated and a central passage leading to a dispensing nozzle. A chamber between the crucible bores and the central passage is sealed by a flexible membrane which is centrally clamped to a valve actuating rod that can be moved longitudinally via flexure of the membrane. A region behind the flexible membrane is sealed and vented to the system vacuum chamber whereby the enclosure within which the gas is generated is isolated.

Abstract: A plasma generation system comprises a two-by-two or larger array of alternating magnetic poles set proximate to an insulating window in a chamber containing a process gas. The magnetic poles are ferromagnetic core coils driven by a radio frequency power source at sufficient energies to generate a plasma within the process gas chamber. The magnetic poles are included in ferromagnetic core coils that are wired to the radio frequency power source such that each magnetic pole is surrounded equally in the plane of the insulating window by adjacent magnetic poles of opposite magnetic polarity and uniform magnitudes. In a two-by-two array, the two sets of opposite corners have opposite magnetic polarities.

Abstract: A semiconductor device fabrication apparatus includes a thermal treatment device for thermally processing a semiconductor substrate, a first oxygen monitor for monitoring the density of oxygen in said thermal treatment device, a load-lock chamber separably coupled to said thermal treatment device for housing the semiconductor substrate before thermal treatment thereof by said thermal treatment device, and a second oxygen monitor for monitoring the density of oxygen in said load-lock chamber. First, the semiconductor substrate is introduced into the load-lock chamber, and then the load-lock chamber is evacuated. Thereafter, the density of oxygen in the load-lock chamber is measured by the second oxygen monitor, and the thermal treatment device is evacuated, after which the density of oxygen in the thermal treatment device is measured by the first oxygen monitor.

Abstract: The photoelectrochemical oxidation and dissolution of silicon (Si) is performed in the absence of water and oxygen. Etch rates and photocurrents in an anhydrous HF-acetonitrile (MeCN) solution are directly proportional to light intensity up to at least 600 mW/cm2, producing a spatially selective etch rate of greater than 4 .mu.m/min. Four electron transfer reactions per silicon molecule occur with a quantum yield greater than 3.3 due to electron injection from high energy reaction intermediates. Further, the electrochemical oxidation of p-doped silicon in HF-MeCN results in the formation of porous silicon which electroluminescence in an aqueous solution. In an aprotic electrolyte, where tetrabutylammonium tetrafluoroborate (TBAFB) is used as both the supporting electrolyte and source of fluoride in MeCN, photo-induced etching of n-doped silicon occurs at quantum efficiency of 1.9. This indicates that the oxidation and dissolution mechanism of Si in MeCN can occur without protons.

Abstract: Copper etchant solution additives for use with an aqueous alkaline ammoniacal cupric chloride etching bath include several compounds, each of which is shown to stabilize the copper(I) state. The compounds discovered by the present invention include iodide ions such as potassium iodide, ammonium iodide, sodium iodide, calcium iodide and magnesium iodide. Other copper(I) stabilizers discovered by the present invention include certain water soluble salts containing sulfur such as a thiocyanate ion (e.g. ammonium thiocyanate, potassium thiocyanate, sodium thiocyanate, magnesium thiocyanate, and calcium thiocyanate) and a thiosulfate ion (e.g. ammonium thiosulfate, potassium thiosulfate, sodium thiosulfate, magnesium thiosulfate, and calcium thiosulfate). Etching rates for alkaline ammoniacal cupric chloride with different concentrations of potassium iodide, ammonium thiocyanate, and sodium thiosulfate were studied.

Abstract: A method and apparatus for monitoring and controlling reactant vapors prior to chemical vapor deposition (CVD). The reactant vapors are monitored at full concentration without sampling as they are transported to a CVD reactor. Contaminants detected cause a process controller to switch the transport path to direct reactant vapors to a system pump.

Abstract: A tool for etching at least one selected area of a silicon dixoide layer on a wafer. The tool includes a container which is partially filled with hydrofluoric (HF) acid. The tool further includes a template having an aperture extending between each selected area and the container. Vapors of the HF acid pass through each aperture to contact and etch each selected area in order to expose a test die on the wafer. An O-ring is associated with each selected area for sealing each of the selected areas from the remaining areas on the silicon dioxide layer such that substantially only the selected areas are etched by the vapors.

Abstract: Described is a method of manufacturing a silicious micro-valve comprising the steps of providing a first silicious substrate; removing a portion of the first substrate to reveal the 111 planes of the first substrate; drawing an epitaxial layer to conform to the 111 planes of the first substrate; and assembling the first substrate and the epitaxial layer as two separate identical pieces to form a micro-valve having 111 planes.

Abstract: After trench formation on a semiconductor wafer (14) using a hard trench mask containing a phosphosilicate glass top layer and an underlying thermal oxide layer, the phosphosilicate glass layer may be removed without substantially etching the thermal oxide layer. The wafer temperature is increased to at least 40.degree. C. (36) prior to etching with an HF/H.sub.2 O vapor (40-44).

Abstract: According to the present invention, a method is provided for forming contact vias in an integrated circuit. Initially, a first protective layer is formed on an insulating layer, and an opening is created through the insulating layer where a contact is to be made. A conductive layer is deposited over the protective layer and partially fills the opening, forming a conductive plug in the opening. A second protective layer is then formed over the conductive plug. Portions of the conductive layer which were formed over the first protective layer are removed. During removal of those portions of the conductive layer, the second protective layer protects the conductive plug from damage. The first and second protective layers are then removed, leaving the conductive plug in the opening in the insulating layer. A conductive contact can now be made by depositing a second conductive layer over the conductive plug.

Abstract: A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.

Abstract: When a ZnSe, ZnTe or ZnSSe or Zn.sub.1-a Mg.sub.a S.sub.b Se.sub.1-b (0<a<1, 0<b<1) layer provided on a Zn.sub.1-x Mg.sub.x S.sub.y Se.sub.1-y (0<x<1, 0<y<1, a<x) layer is selectively etched by a dry etching method such as an RIE method, the Zn.sub.1-x Mg.sub.x S.sub.y Se.sub.1-y layer is used as an etching stoppig layer. Thus, selective etching of the ZnSe, ZnTe, ZnSSe or Zn.sub.1-a Mg.sub.a S.sub.b Se.sub.1-b layer can be conducted with excellent controllability and reproducibility.

Abstract: A semiconductor wafer polisher of the present invention for polishing at least one semiconductor wafer to flatten a first face of the wafer and reduce the thickness of the wafer from an initial thickness t.sub.1 to a predetermined final thickness t.sub.2. The polisher comprises a first surface including a polishing surface portion, a second surface including a second surface portion, and a wafer carrier for holding the semiconductor wafer between the polishing surface portion and the second surface portion. At least one polishing limiter is between the first and second surfaces for limiting the reduction in thickness of the wafer. The wafer carrier and polishing limiter are integrally formed such that the polishing limiter and wafer carrier constitute a single unitary piece.

Abstract: Graphite formation on a diamond surface during laser etching is inhibited or the graphite is removed by contact with a gaseous material such as elemental hydrogen, elemental oxygen, an inert gas or a source of hydroxyl radicals. Preferably, the article being etched is cooled and maintained in an inert atmosphere during etching.

Abstract: This invention includes a method of making a bridge-supported accelerometer structure. A first wafer is worked, preferably by bulk micromachining, to provide a proof mass supported by a thin membrane on all sides. The thin membrane has the same thickness as the bridges to be defined therein. The first wafer is bonded to a second wafer having a cavity formed therein. The first wafer is then worked, preferably by plasma etching, to delineate bridges in the thin membrane. The cavity in the second wafer provides damping of the proof mass which reduced bridge breakage as portions of the thin membrane are removed leaving the final bridge-supported accelerometer structure. Combining the two wafers together prior to delineating the bridge provides for handling and processing of a much less fragile structure than the first wafer alone with bridges delineated therein.

Abstract: An etching method for etching a sendust film formed on a substrate is disclosed. In this method, a mixture of acid solutions of nitric acid and hydrochloric acid is used as an etching liquid. The etching is desirably effected while the sendust film is directly or indirectly held in electrical connection with a ferrite member, with an area of a portion of the ferrite member which contacts the etching liquid being twice to twelve times a total area of etched portions of the sendust film. Also disclosed is a method for pattern-etching a sendust film, and a chromium base film formed between the sendust film and a substrate, which includes the steps of: (a) etching the sendust film to form a predetermined sendust pattern; and (b) etching the chromium base film to form a chromium pattern which conforms to the predetermined sendust pattern, such that the chromium base film is directly or indirectly held in electrical connection with a chromium bulk.

Abstract: A method has been developed for the removal of silicon nitride and silicon dioxide, or other semiconductor materials from a surface of a wafer or CVD reactor. The method uses NF.sub.3, mixed with an electropositive diluent, preferably argon, at a given range of concentration, pressure, flowrate, and power to obtain the fastest possible etch rates. The etch rates of the film being processed can be caused to increase even as the concentration of NF.sub.3 in the diluent is decreased by choosing the proper diluent and operating conditions. Not only does this method increase the etch rate, thereby increasing the throughput of the reactor using this process, it also accomplishes this task at low concentrations of NF3 resulting in a lower cost.

Abstract: A method of producing a silicon membrane has a step of forming an etch stop layer on an upper surface of a silicon substrate having lower and upper opposing surfaces, the etch stop layer comprising an alloy of silicon and at least one other Group IV element. The method of producing a silicon membrane has another step of forming a cap layer on the etch stop layer, the cap layer having lower and upper opposing surfaces with the lower surface contacting the etch stop layer. The method of producing a silicon membrane has a further step of removing a portion of the silicon substrate at a time when the upper surface of the cap layer is exposed, the portion of the silicon substrate being removed extending from the upper surface of the silicon substrate to the lower surface of the silicon substrate to thereby define an exposed portion of the etch stop layer. The exposed portion of the etch stop layer may be removed.

Abstract: In a rapid thermal processing (RTP) of a large-diameter wafer, a wafer is heat treated by an upper high-temperature furnace and a lower low-temperature furnace, which are separated from and can be brought into close contact with one another by a relative vertical position adjusting means. The upper high-temperature furnace has an open bottom which is shut by an openable, heat insulating shutter. Height of the apparatus as a whole can be shortened.