Patents Examined by José R. Díaz
  • Patent number: 12033989
    Abstract: Discussed is a display device, including a substrate having an assembly region and a non-assembly region, semiconductor light emitting devices arranged on the substrate, a first wiring electrode and a second wiring electrode extended from each of the semiconductor light emitting devices, respectively, to supply an electric signal to the semiconductor light emitting devices, pair electrodes arranged on the substrate to generate an electric field when an electric current is supplied, and provided with first and second pair electrodes disposed on an opposite side to the first and second wiring electrodes with respect to the semiconductor light emitting devices, a dielectric layer disposed on the pair electrodes, and bus electrodes electrically connected to the pair electrodes, wherein the pair electrodes are arranged in parallel to each other along a direction in the assembly region, and wherein the bus electrodes are disposed in the non-assembly region.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: July 9, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Juchan Choi, Changseo Park, Bongchu Shim, Kiseong Jeon
  • Patent number: 12034059
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Patent number: 12033858
    Abstract: A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: July 9, 2024
    Assignee: SK hynix Inc
    Inventor: Young Gwang Yoon
  • Patent number: 12021115
    Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: June 25, 2024
    Assignee: Microchip Technology Incorporated
    Inventor: Yaojian Leng
  • Patent number: 12021114
    Abstract: The present disclosure provides a semiconductor structure with a single side capacitor. The semiconductor structure includes a substrate having a first landing pad therein, and a first capacitor disposed over the substrate. The first capacitor includes: a first electrode, disposed over and extending vertically away from the first landing pad; a first dielectric layer, at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode, surrounding the first dielectric layer and the first electrode.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 25, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Min Chou, Shih-Fan Kuan
  • Patent number: 12022657
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: June 25, 2024
    Assignee: Kioxia Corporation
    Inventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
  • Patent number: 12015051
    Abstract: A semiconductor device has a substrate and a first semiconductor layer with a high resistivity, such as an epitaxial layer with a resistivity in the range of 3000-5000 ohms/cm2, formed over the substrate. A second semiconductor layer is formed at least partially in the first semiconductor layer. A capacitor is formed at least partially over the first semiconductor layer. The capacitor has a plurality of trenches extending through the first semiconductor layer and into the substrate, and a first insulating layer formed in the trench. The trenches can be parallel, serpentine, or other geometric shape. The capacitor also has a second insulating layer formed over the first insulating layer, and a polysilicon layer formed over the second insulating layer. A conductive layer is formed over the capacitor. The first semiconductor layer with high resistivity provides a vertical path to discharge high voltage events incident on the capacitor.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: June 18, 2024
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: James J. Brogle, Timothy E. Boles
  • Patent number: 12015052
    Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 18, 2024
    Assignee: Microchip Technology Incorporated
    Inventor: Yaojian Leng
  • Patent number: 11987495
    Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 21, 2024
    Assignee: SiTime Corporation
    Inventors: Pavan Gupta, Aaron Partridge, Markus Lutz
  • Patent number: 11985828
    Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: May 14, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Tatsunori Inoue
  • Patent number: 11985807
    Abstract: A method for manufacturing a semiconductor structure includes: a first mask layer is formed on a dielectric layer, in which a first etching hole extending along a first direction parallel to the dielectric layer is formed in the first mask layer; a side of the first mask layer away from the dielectric layer is planarized; a second mask layer is formed on the first mask layer, in which a second etching hole extending along a second direction parallel to the dielectric layer is formed in the second mask layer, the first etching hole and the second etching hole constitute an etching hole; and the dielectric layer is etched along the etching hole to form the capacitor hole.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Sen Li, Tao Liu
  • Patent number: 11973106
    Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: April 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Hee Song, Dong Hyun Lee, Kyung Woong Park, Cheol Hwan Park, Ki Vin Im
  • Patent number: 11967611
    Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Yi Yang Wei, Fa-Shen Jiang, Bi-Shen Lee, Hsun-Chung Kuang
  • Patent number: 11961813
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 16, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11961883
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: April 16, 2024
    Assignee: ROHM CO. LTD.
    Inventor: Jun Takaoka
  • Patent number: 11955568
    Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 9, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Larry Buffle, Frédéric Voiron, Sophie Archambault
  • Patent number: 11955511
    Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes an array area and a peripheral area adjacent to each other, and the array area includes a buffer area connected to the peripheral area; forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate, forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer area; removing the third dielectric layer through a wet etching process; and etching the second supporting layer in the peripheral area after removing the third dielectric layer.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shuangshuang Wu
  • Patent number: 11948969
    Abstract: A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming Chyi Liu, Chun-Tsung Kuo
  • Patent number: 11942553
    Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Kyeong Jeong, Yun Heub Song, Chang Hwan Choi, Hyeon Joo Seul
  • Patent number: 11939216
    Abstract: A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: March 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Stephan Helbig, Adolf Koller