Patents Examined by José R. Díaz
  • Patent number: 11031433
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 8, 2021
    Assignee: STMicroelectronics (Crolles) SAS
    Inventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
  • Patent number: 11018224
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 11018113
    Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lipu Kris Chuang, Chung-Hao Tsai, Hsin-Yu Pan, Yi-Che Chiang, Chien-Chang Lin
  • Patent number: 11011485
    Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Choi, Doo Hwan Lee, Joo Young Choi, Sung Han, Byung Ho Kim
  • Patent number: 11011575
    Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Yu-Chun Chen, Chiu-Jung Chiu
  • Patent number: 11011456
    Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
  • Patent number: 11004807
    Abstract: A method of manufacturing a laminated substrate including an insulation substrate comprised of ceramic, and a front electrode formed on a front surface of the insulation substrate, a semiconductor element being mountable on a front surface of the front electrode, including forming the front electrode on the front surface of the insulation substrate, and before or after the forming the front electrode, applying laser processing to the front surface of the insulation substrate at an outer peripheral area of the front electrode to modify a conductive property of the front surface of the insulation substrate to have electrical conductivity.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 11, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keisuke Yamashiro
  • Patent number: 10998263
    Abstract: An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jim Shih-Chun Liang, Naftali E. Lustig, Baozhen Li, Ning Lu
  • Patent number: 10998194
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Patent number: 10998421
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Patent number: 10998348
    Abstract: A display apparatus includes a substrate including a display area, in which gate lines and data lines are disposed, and a non-display area, in which a gate driver and a pad part are disposed. A gate insulating layer is on the substrate. Data link lines are on the gate insulating layer to connect data pads of the pad part to the data lines, and an interlayer insulating layer is on the data link lines. Gate voltage supply lines are on the interlayer insulating layer to connect the gate driver with the gate lines. A protective layer is on the interlayer insulating layer to cover the gate voltage supply lines, the protective layer including an opening for exposing the interlayer insulating layer of an area overlapping the data link lines.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 4, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Hyun-Chul Um, Jong-Chan Park
  • Patent number: 10985119
    Abstract: The present invention includes a first semiconductor chip, a second semiconductor chip, a first inductor, a second inductor, a second capacitor, protective diodes, and a third inductor. A field effect transistor includes a gate terminal, a drain terminal, and a source terminal connected to a ground terminal. The second semiconductor chip includes an input terminal and an output terminal connected in a direct current manner, and includes a first capacitor connected to the input terminal and to the ground terminal. The first inductor is connected between the output terminal and the gate terminal. The second inductor includes a first terminal connected to the input terminal. The second capacitor is connected between a second terminal of the second inductor and the ground terminal. Protective diodes are connected in series in a forward direction, and each has a cathode, and an anode connected to the ground terminal. The third inductor is connected between the cathode and the second terminal.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 20, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshinobu Sasaki
  • Patent number: 10978234
    Abstract: A magnetic stack includes a first element including a ferromagnetic layer; a second element including a metal layer able to confer on the assembly formed by the first and the second elements a magnetic anisotropy perpendicular to the plane of the layers. The first element further includes a refractory metal material, the second element being arranged on the first element.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 13, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
    Inventors: Jyotirmoy Chatterjee, Paulo Veloso Coelho, Bernard Dieny, Ricardo Sousa, Lucian Prejbeanu
  • Patent number: 10978416
    Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Robert K. Leidy, Jeffrey C. Maling
  • Patent number: 10978782
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 10971545
    Abstract: A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kevin Conley, Sarin A. Deshpande
  • Patent number: 10971603
    Abstract: A method for producing a thin-film-transistor involves forming a flexible substrate on a rigid substrate, forming a plurality of fins and trenches in a structural layer arranged on the flexible substrate, forming a wavy gate layer, channel layer, source contact layer, and drain contact layer on each of the plurality of fins and each of a plurality of trenches of the structural layer, and removing the plurality of fins and trenches having the wavy gate, channel, source contact, and drain contact layers from the rigid substrate.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 6, 2021
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Amir Nabil Hanna, Muhammad Mustafa Hussain
  • Patent number: 10964764
    Abstract: A display panel and a method of manufacturing thereof are provided. The pixel defining block is formed by one-time exposing the column spacer column and the bank with a halftone mask, thereby omitting the process of individually forming the bank, and manufacturing time and manufacturing cost are reduced. The organic functional layer disposed above the bank is not directly contacted with the first electrode due to the bank structure, and the bank causes the defined region to be disconnected from the first electrode, and no current flows through the defined region. Thus, the defined region does not emit light, and the pixel region emits uniform light. The material of the bank is an organic photoresist, so hydrogen and oxygen are not introduced into the bank, and therefore not affect the thin film transistor, and improves stability of the display panel.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 30, 2021
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Fen Zhou, Jia Tang
  • Patent number: 10957671
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 23, 2021
    Assignee: Intel Deutschland GMBH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Patent number: 10950705
    Abstract: An active matrix substrate includes a peripheral circuit including a TFT (30A) supported on a substrate (1). When viewed in a direction normal to the substrate (1), a first gate electrode (3) of the TFT (30A) includes a first edge portion and a second edge portion (3e1, 3e2) opposing each other. The first edge portion and the second edge portion extend across an oxide semiconductor layer (7) in a channel width direction. At least one of the first edge portion and the second edge portion includes, in a region overlapping with the oxide semiconductor layer (7), a first recess portion (40) recessed in a channel length direction and a first part (41) adjacent to the first recess portion in the channel width direction. When viewed in the direction normal to the substrate (1), a source electrode (8) or a drain electrode (9) of the TFT (30A) overlaps with at least a part of the first recess portion (40) and at least a part of the first part (41).
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: March 16, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tadayoshi Miyamoto