Abstract: A light emitting device includes a substrate, a light emitting element, and a protective element. The substrate includes a support member and a plurality of wirings disposed on an upper surface of the support member. The substrate has a first side extending in a first direction and a second side opposite to the first side. The light emitting element is disposed on an upper surface of the substrate, and the protective element is disposed on the upper surface of the substrate. The plurality of wirings has a plurality of external connecting portions disposed adjacent to the first side and arranged in the first direction in a plan view. The protective element is disposed between the light emitting element and the second side of the substrate.

Abstract: A capacitor may comprise a substrate and a first electrically conductive electrode layer. A metal oxide layer may be deposited on at least one of the substrate or the first electrically conductive electrode layer. A proximal region of the metal oxide may comprise a stoichiometric, dielectric, oxygen vacancy-free portion of the metal oxide. The proximal region may be in communication with the first electrically conductive electrode layer. A distal region of the metal oxide may comprise a constant oxygen vacancy portion. The distal region may be in communication with a second electrically conductive electrode layer. The metal oxide may comprise a gradient region comprising a substantially stoichiometric metal oxide portion and a substantially constant oxygen vacancy portion. The gradient region may comprise an increasing oxygen vacancy gradient from the proximal region to the distal region. The second electrically conductive electrode layer may be deposited on the distal region.

Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer includes a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·1015 cm?3, and a layer thickness of at least 10 ?m, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 ?m to 2 ?m and a dopant concentration of at least 1·1019 cm?3.

Abstract: A semiconductor memory device includes a plurality of bit line structures including bit lines extending in parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of a first landing pad, a second landing pad, and a third landing pad, which are adjacent to each other from among the plurality of landing pads, are connected by a scalene triangle.

Abstract: A method for forming a capacitor array includes depositing a first nitride layer, a first oxide layer, and a second nitride layer in sequence over first and second contacts on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form first and second openings exposing the first and second contacts; conformally depositing a bottom electrode layer over the first and second nitride layers and the first oxide layer and on the first and second contacts; etching the second nitride layer and the first oxide layer to form a third opening having a bottom position higher than a top surface of the first nitride layer; removing the first oxide layer through the third opening; forming a capacitor dielectric layer over the bottom electrode layer; forming a top electrode layer over the capacitor dielectric layer.

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

Abstract: A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.

Abstract: A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.

Abstract: Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Abstract: A display apparatus includes: a substrate including a first surface, a second surface opposite the first surface, a display area defined on the first surface, and a non-display area defined on the second surface; a plurality of display elements at the display area on the first surface of the substrate; a driving circuit on the second surface and overlapping with the display area of the substrate; a first conductive pattern on the second surface of the substrate; and a second conductive pattern on the first surface of the substrate and connected to the first conductive pattern via a contact hole extending through the substrate. A surface roughness of the second surface of the substrate is greater than a surface roughness of the first surface of the substrate.

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first coil and a second coil of an inductor. The first coil and the second coil are located at different level heights. The first coil includes a first metallic material. The second coil includes a second metallic material. The first metallic material has a different composition from the second metallic material. The second die is bonded to the first die. The second die includes a third coil of the inductor. The inductor extends from the first die to the second die.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.