Abstract: A lead frame includes a plurality of lead portions. At least a part of an upper surface of the lead portion and a sidewall surface of the lead portion is a rough surface having been subjected to roughening treatment. A value of a* in a CIELab color space of the rough surface is within a range from 12 to 19, and a value of b* is within a range from 12 to 17.

Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.

Abstract: Embodiments of present disclosure provide a MIM capacitor including a straining layer on an electrode, and a high-k dielectric layer formed on the straining layer. The straining layer allows the high-k dielectric layer to be highly crystallized without requiring an extra annealing process. The high crystallization of the high-k dielectric layer results in increased the dielectric value (k-value), thus, improving capacitance density in the MIM capacitor. Some embodiments provide a MIM capacitor device including stacked MIM capacitors with symmetrically arranged high-k dielectric layers and straining layers.

Abstract: A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.

Abstract: A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Abstract: A method includes forming first-type deep trenches and second-type deep trenches in a substrate, in which the first-type deep trenches have a first lengthwise direction along a first direction and the second-type deep trenches have a second lengthwise direction along a second direction; forming a capacitor structure over the substrate and in the first-type deep trenches and the second-type deep trenches, in which the capacitor structure includes a first metallic electrode layer, a node dielectric layer over the first metallic electrode layer, and a second metallic electrode layer over the node dielectric layer; and forming a first metal via over the capacitor structure and in contact with the second metallic electrode layer of the capacitor structure, in which a length of the first metal via is greater than a width of the first metal via from a top view.

Abstract: An electroluminescence display having a repair structure is disclosed. The electroluminescence display comprises: a substrate, a buffer layer on the substrate, a repair element, and a pixel including a thin film transistor and a light emitting element. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a gate electrode, and a gate insulating layer between the gate electrode and the semiconductor layer. The light emitting element is connected to the drain electrode. The repair element includes a repair line and a repair electrode. The repair line is disposed between the substrate and the buffer layer, and includes a first metal layer on the substrate, and a second metal layer on the first metal layer. The repair electrode is on the buffer layer and the gate insulating layer that covers the repair line and the repair electrode overlaps the repair line.

Abstract: A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; a second electrode layer contacting the dielectric film without contacting the metal foil; and an insulating member provided on the upper surface of the metal foil to surround the first and second electrode layers. The metal foil has an outer peripheral area which is positioned outside an area surrounded by the insulating member and which is not covered with the first and second electrode layers. A height of the electrode layer is equal to or higher than a height of the insulating member. This makes the outer peripheral portion of the thin film capacitor have a step-like shape.

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Abstract: An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Abstract: According to one aspect of a technique of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: (A) forming a film containing a predetermined element and nitrogen on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes: (a) forming a first layer by supplying a source gas containing the predetermined element and a halogen element to the substrate heated to a first temperature; (b) forming a second layer by modifying the first layer by supplying a plasma-excited first modification gas containing hydrogen free of nitrogen; and (c) forming a third layer by modifying the second layer by supplying a plasma-excited second modification gas containing nitrogen and hydrogen. A supply time TH of supplying the first modification gas in (b) is set to be longer than a supply time TN of supplying the second modification gas in (c).

Abstract: A probe grinding device by acoustic positioning includes a fixing base, a grinding base, a rotating module, a motor module, a moving module, a processing module, an acoustic sensing module, and a memory module. The fixing base fixes a probe card. The acoustic sensing module generates and transmits an acoustic sensing signal to the processing module. The memory module stores a grinding audio of a grinding audio data. When the processing module drives the rotating module and the moving module via the motor module, the processing module determines whether the acoustic sensing signal matches the grinding audio. When the acoustic sensing signal matches the grinding audio, the processing module drives the moving module to slowly move the grinding base to avoid damaging the probes.

Abstract: Provided is display device comprising a substrate; a first semiconductor layer disposed on the substrate and having a plurality of transistors; a second semiconductor layer disposed on the first semiconductor layer and having a plurality of transistors; a first data conductive layer disposed on the second semiconductor layer; a first metal layer disposed on the first data conductive layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer includes a first storage electrode and a first input electrode, the second metal layer includes a second storage electrode and a second input electrode, the first storage electrode and the second storage electrode configure a storage capacitor, and the first input electrode and the second input electrode configure an input capacitor.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.

Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.