Patents Examined by José R. Diaz
  • Patent number: 10802545
    Abstract: The present disclosure relates to a display panel including a display area that can be stretched by including a plurality of stretching units and a peripheral area positioned at an edge of the display area. Each of the stretching units includes: a plurality of islands separately disposed to include a plurality of pixels disposed therein; a plurality of bridges extended from the islands to connect adjacent islands or to connect the islands with the peripheral area; and a plurality of openings disposed adjacent to the bridges, between the bridges, and between the bridges and the islands, wherein areas of the islands are gradually increased toward the peripheral area.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Ho Hong, Hye Jin Joo, Gun Mo Kim, Il Gon Kim, Jae Min Shin
  • Patent number: 10797158
    Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Patent number: 10790388
    Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Koshimizu, Komaki Inoue, Hideki Niwayama
  • Patent number: 10788446
    Abstract: A semiconductor device includes a first passivation layer disposed on a semiconductor base. The semiconductor device further includes a dielectric layer disposed on the first passivation layer. The semiconductor device further includes a plurality of pillars disposed in an opening in the dielectric layer and the first passivation layer and from a top surface of the semiconductor base. The semiconductor device further includes a metal layer disposed on the exterior surfaces of the plurality of pillars and sidewalls of the dielectric layer and the first passivation layer and on the exposed top surface of the semiconductor base. The semiconductor device further includes a second passivation layer disposed on the metal layer and a top surface of the semiconductor device; wherein the second passivation layer has an electrical charge.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 10790257
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Patent number: 10784369
    Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, a source region and a drain region disposed on the semiconductor substrate. The drain region has a second conductivity type that is the opposite of the first conductivity type, and the source region includes a part having the first conductivity type and another part having the second conductivity type. The device includes a first and a second isolation structures disposed on two opposite sides of the drain region. The first isolation structure is between the source and the drain region. The device includes a first well region disposed below the second isolation structure. The top surface of the first well region is adjacent to the bottom surface of the second isolation structure. In addition, the device includes a first buried layer disposed in the semiconductor substrate and that overlaps the first well region.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 22, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Vivek Ningaraju, Vinay Suresh, Po-An Chen
  • Patent number: 10770687
    Abstract: A standard direction (S) is a horizontal direction (a direction along X direction in the drawing). A base material (200) is supported by a frame body (250) so that a second surface (204) of the base material (200) is oriented obliquely upward from the standard direction (S). Thereby, a reference direction (R) is oriented obliquely upward from the standard direction (S). Light from the light-emitting system (20) has standard chromaticity in the standard direction (S). In addition, the light from the light-emitting system (20) has first chromaticity and second chromaticity in a first side direction (S1) and a second side direction (S2), respectively, the first side direction (S1) and the second side direction (S2) being symmetric with respect to the standard direction (S). A difference between the first chromaticity and the standard chromaticity is smaller than a difference between the second chromaticity and the standard chromaticity.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 8, 2020
    Assignee: PIONEER CORPORATION
    Inventor: Hiroaki Kitahara
  • Patent number: 10770356
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Patent number: 10741637
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 11, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 10741580
    Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer and a second conductive layer arranged in a first direction crossing a surface of the substrate and extending in a second direction crossing the first direction, the first conductive layer being closer to the substrate than the second conductive layer, a length in the second direction of the first conductive layer being greater than the length of the second conductive layer; a first semiconductor film extending in the first direction and facing the first and second conductive layers; a second semiconductor film interposed between ends of the first and second conductive layers, extending in the first direction, and facing the first conductive layer; a first wiring farther from the substrate than the first semiconductor film and being electrically connected to the first semiconductor film; and a second wiring farther from the substrate than the second semiconductor film and being electrically connected to the second semiconductor fil
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 10741635
    Abstract: To reduce a possibility of short circuiting between a wiring line that connects to a terminal unit and a pixel electrode, a display device is provided that includes a first lead wiring line that extends from a display area to a frame area while intersecting with an end portion of a flattening film, a second lead wiring line that is in a layer more on an upper side than the first lead wiring line and extends to a terminal unit while coming into contact with and intersecting with a first bank formed in a periphery of a second electrode, and a first wiring line contact part through which the first lead wiring line and the second lead wiring line connect to each other, the first wiring line contact part being provided between an end portion of the flattening film and the first bank.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 11, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Ryosuke Gunji, Hiroki Taniyama, Shinji Ichikawa, Yoshihiro Nakada, Hiroharu Jinmura, Akira Inoue
  • Patent number: 10734372
    Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Stuart A. Sieg, Junli Wang
  • Patent number: 10723617
    Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 28, 2020
    Assignee: SiTime Corporation
    Inventors: Pavan Gupta, Aaron Partridge, Markus Lutz
  • Patent number: 10714498
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer; a second interconnect layer adjacent to the first interconnect layer; a semiconductor layer between the first and second interconnect layers; a first charge storage layer between the first interconnect layer and the semiconductor layer; and a second charge storage layer between the second interconnect layer and the semiconductor layer. A first distance between the first and second interconnect layers is shorter than a second distance between the first and second charge storage layers.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 14, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Harumi Seki, Yuichiro Mitani, Takamitsu Ishihara
  • Patent number: 10700057
    Abstract: The disclosed embodiments include an ESD robust transistor with a compound-SCR protection. The transistor may include a semiconductor substrate having a first conductivity type, a drain region coupled with the semiconductor substrate having a drain SCR component with a first drain region of the first conductivity type and a second drain region of the second conductivity type. The transistor may also include a source coupled with the semiconductor substrate, a channel region of the second conductivity type, and a gate coupled with the channel region having SCR components with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR components and the gate SCR components may create a low resistance discharge path along the channel region that activates in response to the ESD such that the ESD discharges through the transistor without causing damage to the transistor.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash Elhami Khorasani, Mark Griswold
  • Patent number: 10672941
    Abstract: A method (200) for fabricating thin-film optoelectronic devices (100), the method comprising: providing a substrate (110), forming a back-contact layer (120); forming at least one absorber layer (130) made of an ABC chalcogenide material, adding at least one alkali metal (235), and forming at least one cavity (236, 610, 612, 613) at the surface of the absorber layer wherein forming of said at least one cavity is by dissolving away from said surface of the absorber layer at least one crystal aggregate comprising at least one alkali crystal comprising at least one alkali metal. The method (200) is advantageous for more environmentally-friendly production of photovoltaic devices (100) on flexible substrates with high photovoltaic conversion efficiency and faster production rate.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: June 2, 2020
    Assignees: FLISOM AG, EMPA
    Inventors: Patrick Reinhard, Fabian Pianezzi, Benjamin Bissig, Stephan Buecheler, Ayodhya Nath Tiwari
  • Patent number: 10672719
    Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 ?m to 70 ?m.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang Heon Hur, Jong Man Kim, Kyung Ho Lee, Han Kim
  • Patent number: 10672752
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10672870
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Long-Jie Hong
  • Patent number: 10672901
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Satoshi Suzuki, Simon John Molloy