Abstract: A semiconductor device includes a first gate electrode structure having a first gate insulating layer on a substrate and a first gate electrode on the first gate insulating layer. A first spacer structure includes a first spacer and a second spacer on side walls of the first gate electrode structure. The first spacer is disposed between the second spacer and the first gate electrode. A source/drain region is disposed on opposite sides of the first gate electrode structure. The first gate electrode includes a lower part of the first gate electrode, an upper part of the first gate electrode disposed on the lower part of the first gate electrode, and the first spacer is disposed on the side wall of the upper pan of the first gate electrode and is not disposed on the side wall of the lower part of the first gate electrode.

Abstract: A magnetic field magnetic field sensor and method of making the sensor. The sensor and method of making the sensor may comprise a material or structure that prevents the admission of light in certain wavelengths to enhance the stability of the magnetic field sensor over a period of time. The sensor and method of making the sensor may comprise an adsorption prevention layer which protects the semiconductor portion of the magnetic. The sensor may also comprise an insulating layer formed between semiconductor layers and a substrate layer.

Abstract: An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Abstract: A method of manufacturing a solar cell, includes forming a rounded uneven member having a rounded end portion at a second surface of a semiconductor substrate having a first surface and the second surface opposite to each other, forming conductive regions comprising forming a first conductive region at the first surface of the semiconductor substrate and forming a second conductive region on the second surface of the semiconductor substrate, wherein the second conductive region comprises a semiconductor layer different and separated from the semiconductor substrate and forming electrodes comprising forming a first electrode electrically connected to the first conductive region and forming a second electrode electrically connected to the second conductive region.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

Abstract: A manufacturing method for a deep trench, the method includes forming a first trench in a substrate and performing a first cycle and a second cycle. Each comprising performing a passivation operation forming a passivation film on a sidewall and a bottom surface of the first trench, performing a first etching with a first bias power to remove the passivation film formed on the bottom surface of the first trench to expose the bottom surface of the first trench, and performing a second etching with a second bias power etching the exposed bottom surface of the first trench to form a second trench disposed below the first trench. The first bias power and the second bias power in the second cycle is greater than the first bias power and the second bias power in the first cycle, respectively.

Abstract: A preparation method of a semiconductor structure includes: providing a substrate, and forming a groove on the substrate by etching; forming a first dielectric layer on a side wall of the groove; forming a first electrode on the bottom of the groove and on an inner surface of the first dielectric layer; forming a second dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the second dielectric layer.

Abstract: The present invention discloses a method for preparing a bifacial PERC solar cell. The present invention has high photoelectric conversion efficiency, high appearance quality, and high EL yield, and could solve the problems of both scratching and undesirable deposition.

Abstract: The present invention discloses a method for preparing bendable nanopaper-based flexible solar cells by 3D aerogel jet printing. In this method, firstly all-cellulose paper is soaked in ionic liquid, and quickly partially dissolved and regenerated under the condition of hot pressing to produce nanopaper with high transmittance and high haze; and then a 3D aerogel jet printer is used to precisely print the respective layers of a solar cell on the surface of the nanopaper as a flexible substrate material, wherein the solar cell comprises an anode PFN/Ag NWs, an active layer CuPc/C60/PTCBI/BCP and a cathode MoO3/Ag/MoO3, and the thickness of each layer is precisely controlled by setting the parameters of the 3D printer. The electrode grid line on the surface of the prepared paper flexible solar cell has a width less than 10 ?m and a thickness less than 20 nm.

Abstract: A display device includes a substrate, a circuit layer on the substrate, a display layer on the circuit layer, at least one hole in a display area of the substrate that penetrates the substrate, the circuit layer, and the display layer, and at least two grooves that surround the at least one hole, where each of the at least two grooves has an undercut structure. The substrate includes a first substrate, a first inorganic layer, a second substrate, and a second inorganic layer, which are sequentially stacked, and each of the at least two grooves extends down from the display layer into the second substrate.

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Abstract: A thin film transistor array substrate having a pixel arrangement structure includes a first sub-pixel for displaying a first color and a second sub-pixel for displaying a second color alternately located in a first column, and a third sub-pixel for displaying a third color in a second column adjacent to the first column, and via holes of the first through third sub-pixels in a same row are at different positions.

Abstract: A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.

Abstract: A semiconductor device includes a work piece comprising a first material, a first side, a second side opposite to the first side, and a first coefficient of thermal expansion (first CTE). Recesses extend into the work piece from the first side and includes a pattern. A second material having a second CTE is within the recesses and is over the first material between the recesses; and A third material having a third CTE is over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a first recess, a second recess, a passivation layer, and an etch mask layer. The group III-V barrier layer includes a thinner portion, a first thicker portion and a second thicker portion in the active region, the thinner portion surrounds the first thicker portion, and the second thicker portion surrounds the thinner portion. The first recess is disposed in the group III-V barrier layer in the active region. The second recess is disposed in the group III-V barrier layer in the isolation region.

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.