Abstract: Provided are a display device, a drive circuit, and a driving method. An accurate threshold voltage compensation value is calculated by finely and incrementally correcting the threshold voltage compensation value in real time during display driving. Consequently, a threshold voltage is accurately and rapidly compensated for.

Abstract: The present disclosure discloses a display driving apparatus in which the consumption power of a chip is optimized through control for each output channel of the chip. The display driving apparatus includes a consumption current control circuit for each output channel. The consumption current control circuit is configured to selectively provide a control current having a high current amount in order to drive an output voltage for the output side of an output buffer in response to a change in the pattern having a great difference between an input voltage and an output voltage.

Abstract: The present disclosure relates to a gate drive circuit. The gate drive circuit includes: cascaded GOA units, first clock signal lines, second clock signal lines, connecting lines and electrostatic protection sub-circuits. The first clock signal lines are used to provide various clock signals to the GOA units. The second clock signal lines are used to, when any of the clock signal lines is broken, replace the broken clock signal line to transmit a corresponding clock signal. The electrostatic protection sub-circuits are electrically connected to corresponding first clock signal lines or corresponding second clock signal lines through the connecting lines. Orthographic projections of the connecting lines on a plane where corresponding first clock signal lines or corresponding second clock signal lines are located intersect with the corresponding first clock signal lines and the corresponding second clock signal lines, respectively.

Abstract: A display device and a driving circuit enable to detect the crack for each display panel block by independently controlling each data driving circuit in case of multi data driving circuit and to provide a display device and a driving circuit enable to detect not only fine cracks but also disconnection by sequentially comparing a voltage of the display panel block with a reference voltage using a plurality of reference resistors.

Abstract: A display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and generate second output data during a second display update period. The driver circuitry is configured to update a display panel based on the first output data during the first display update period and update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period.

Abstract: The present disclosure provides a driving method for a display panel for displaying multiple frames of image to be displayed, the image to be displayed includes a plurality of image pixel units, the display panel includes a plurality of display pixel units, and the driving method includes the following steps performed when displaying each of frames of image to be displayed: detecting a grayscale value of each image pixel unit in the image to be displayed; determining whether the grayscale value of each image pixel unit is greater than a predetermined value; and providing a predetermined display voltage to a display pixel unit of the display panel corresponding to the image pixel unit, the grayscale value of which is greater than the predetermined value, the predetermined display voltage is lower than a voltage provided when the display pixel unit is driven according to the predetermined value.

Abstract: A display device includes: a plurality of pixels to receive data voltages based on converted grayscales; and a grayscale converter to: calculate first compensation offsets based on positions of the pixels and input grayscales for the pixels; convert the first compensation offsets into second compensation offsets according to a maximum luminance weight based on an input maximum luminance; and calculate the converted grayscales by applying the second compensation offsets to the input grayscales.

Abstract: A display apparatus, in which a black image is provided between real images and one frame period for displaying the black image is set to be shorter than one frame period where each of the real images is displayed, is provided. The display apparatus includes a display panel displaying a black image and a real image, a gate driver supplying gate signals to a plurality of gate lines provided in a display area of the display panel, and a controller controlling a function of the gate driver. A one-frame period for displaying the black image is shorter than a one-frame period where the real image is displayed.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: A display device includes a display panel including a plurality of pixels, a sensing circuit to measure a sensing current value of each of the pixels during a frame period, wherein the frame period includes an active period and a blank period following the active period, and a driving controller to calculate a deterioration weight based on the sensing current value and a reference current value, and to generate output image data by applying the deterioration weight to input image data.

Abstract: The embodiments of the present disclosure provide a gate driving circuit, a display device, and a display control method. The gate driving circuit includes: a first gate driving sub-circuit configured to output a scan signal and control the first display area to display according to the scan signal; a display area control unit having an input terminal configured to receive the scan signal output by the first gate driving sub-circuit, a control terminal configured to receive a split-screen control signal output by the split-screen control signal terminal, and an output terminal configured to output or not output the scan signal according to the split-screen control signal; and a second gate driving sub-circuit configured to control a display state of the second display area according to whether the scan signal is received or not.

Abstract: Disclosed are a device and method for measuring an organic light emitting diode, which measures an amount of energy for compensating for a burn-in of an organic light emitting diode, by sensing a charged voltage of a sensing line connected to the organic light emitting diode. The device for measuring an organic light emitting diode includes an external current source, and is configured to measure an amount of energy for compensating for a burn-in, by sensing a charged voltage of a parasitic capacitor of a sensing line.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking input circuit, a display input circuit, an output circuit, and a coupling circuit. The blanking input circuit is configured to input a blanking input signal to a control node and is configured to input a blanking signal to a first node in a blanking phase of one frame; the display input circuit is configured to input a display signal to the first node in a display phase of one frame in response to a first clock signal; and the coupling circuit is electrically connected to the control node and is configured to control, by coupling, a level of the control node in response to the blanking signal.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A display panel and an electronic device is provided. A voltage drop value of the clock input transistor of a pull-up module of m1st GOA unit connected to an n1st clock signal line is greater than a voltage drop value of the clock input transistor of a pull-up module of m2nd GOA unit connected to the n2nd clock signal line. Based on this circuit structure, a CK impedance difference existing in 8K ultra-high resolution electronic devices can be alleviated.

Abstract: A display device includes a display panel, a gate driving block which outputs a scan signal to the display panel, a source driving block which outputs a data signal to the display panel, and a controller. In the low-frequency mode, the controller divides the display panel into a first area operated at a first frequency lower than the reference frequency and a second area operated at a second frequency lower than the first frequency according to the image data, the source driving block outputs the data signal to the first area at the first frequency and outputs the data signal to the second area at the second frequency, and the gate driving block outputs a first scan signal to the first area at the first frequency and outputs a second scan signal to the second area at the second frequency.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: A display device: a substrate including a first display area and a second display area; a signal line which overlaps the first display area and the second display area; and a common electrode which overlaps the first display area and the second display area, where the first display area includes a first pixel area, the second display area includes a second pixel area and a transmitting area, the transmitting area includes a first transmitting area and a second transmitting area, which have different transmittances from each other, the common electrode overlaps the first pixel area, the second pixel area and the second transmitting area, and in the second transmitting area, at least a part of the signal line and the common electrode overlap each other.

Abstract: The present disclosure provides a shift register unit, including: a first input sub-circuit configured to conduct a first voltage terminal with a first node under control of a first clock signal terminal; a first output sub-circuit configured to conduct a second voltage terminal with an output terminal under control of the first node; a second input sub-circuit configured to conduct an input terminal with a second node under control of the first clock signal terminal; a second output sub-circuit configured to conduct a second clock signal terminal with the output terminal under control of the second node; a first switching sub-circuit configured to conduct the first clock signal terminal with the first node under control of the second node; a second switching sub-circuit configured to conduct a third clock signal terminal with the storage sub-circuit under control of the first node.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.